Index: firmware/export/s5l8700.h
===================================================================
--- firmware/export/s5l8700.h	(revision 28709)
+++ firmware/export/s5l8700.h	(working copy)
@@ -25,7 +25,7 @@
 #define REG16_PTR_T volatile uint16_t *
 #define REG32_PTR_T volatile uint32_t *
 
-#define TIMER_FREQ  47923200L
+#define TIMER_FREQ  (1843200 * 2 * 109 / 2 / 4)
 
 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
 
Index: firmware/target/arm/s5l8700/system-target.h
===================================================================
--- firmware/target/arm/s5l8700/system-target.h	(revision 28709)
+++ firmware/target/arm/s5l8700/system-target.h	(working copy)
@@ -25,18 +25,18 @@
 #include "mmu-arm.h"
 
 #define CPUFREQ_SLEEP      32768
-#define CPUFREQ_DEFAULT 47923200
-#define CPUFREQ_NORMAL  47923200
-#define CPUFREQ_MAX    191692800
+#define CPUFREQ_MAX     (1843200 * 2 * 109 / 2) /* 200.9 MHz */
+#define CPUFREQ_DEFAULT (CPUFREQ_MAX/4)
+#define CPUFREQ_NORMAL  (CPUFREQ_MAX/4)
 
 #define STORAGE_WANTS_ALIGN
 
-#define inl(a) (*(volatile unsigned long *) (a))
+#define inl(a)    (*(volatile unsigned long *) (a))
 #define outl(a,b) (*(volatile unsigned long *) (b) = (a))
-#define inb(a) (*(volatile unsigned char *) (a))
+#define inb(a)    (*(volatile unsigned char *) (a))
 #define outb(a,b) (*(volatile unsigned char *) (b) = (a))
-#define inw(a) (*(volatile unsigned short *) (a))
-#define outw(a,b) (*(volatile unsigned short *) (b) = (a))
+#define inw(a)    (*(volatile unsigned short*) (a))
+#define outw(a,b) (*(volatile unsigned short*) (b) = (a))
 
 static inline void udelay(unsigned usecs)
 {
Index: firmware/target/arm/s5l8700/crt0.S
===================================================================
--- firmware/target/arm/s5l8700/crt0.S	(revision 28709)
+++ firmware/target/arm/s5l8700/crt0.S	(working copy)
@@ -131,7 +131,8 @@
     mov r0, #0
     str r0, [r1,#0x24]  // PLLCON
 #ifdef IPOD_NANO2G
-    ldr r0, =0x21200    // pdiv=2, mdiv=0x12 sdiv=0
+//    ldr r0, =0x021200   // pdiv=2, mdiv=0x12 sdiv=0, 192 MHz
+    ldr r0, =0x006501   // pdiv=0, mdiv=0x65 sdiv=1, 201 MHz
 #else
     ldr r0, =0x1ad200   // pdiv=0x1a, mdiv=0xd2 sdiv=0
 #endif
@@ -146,7 +147,7 @@
     ldr r0, [r1,#0x20]  // PLLLOCK
     tst r0, #1
     beq 1b
-    mov r0, #0x280
+    mov r0, #0x280      // 0x280 = HCLK / 2
     str r0, [r1,#0x3c]  // CLKCON2
     ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
     str r0, [r1]        // CLKCON
@@ -252,6 +253,10 @@
     orr r0, r0, #0x1000
     mcr 15, 0, r0, c1, c0, 0 // re-enable protection unit and caches
 
+    ldr r1, =0x38200000
+    ldr r0, =0x006A49A5 // default: settings from Apple FW (96 MHz HCLK)
+    str r0, [r1, #0x10] // MIUSDPARA
+
 #else
 
     ldr r1, =0x3c500000
Index: firmware/target/arm/s5l8700/kernel-s5l8700.c
===================================================================
--- firmware/target/arm/s5l8700/kernel-s5l8700.c	(revision 28709)
+++ firmware/target/arm/s5l8700/kernel-s5l8700.c	(working copy)
@@ -44,7 +44,10 @@
     
     /* configure timer for 10 kHz */
     TBCMD = (1 << 1);   /* TB_CLR */
-    TBPRE = 300 - 1;    /* prescaler */
+    TBPRE = 314 - 1;    /* prescaler 50 MHz */
+//    TBPRE = 300 - 1;    /* prescaler 48 MHz */
+//    TBPRE = 157 - 1;    /* prescaler 25 MHz */
+//    TBPRE = 150 - 1;    /* prescaler 24 MHz */
     TBCON = (0 << 13) | /* TB_INT1_EN */
             (1 << 12) | /* TB_INT0_EN */
             (0 << 11) | /* TB_START */
Index: firmware/target/arm/s5l8700/system-s5l8700.c
===================================================================
--- firmware/target/arm/s5l8700/system-s5l8700.c	(revision 28709)
+++ firmware/target/arm/s5l8700/system-s5l8700.c	(working copy)
@@ -210,6 +210,9 @@
         pmu_write(0x1e, 0xf);
         /* Allow for voltage to stabilize */
         udelay(100);
+        /* Configure for 100 MHz clock */
+        //MIUSDPARA = 0x0069291D; // RAS2CAS = 2
+        MIUSDPARA = 0x006A491D; // RAS2CAS = 3
         /* FCLK_CPU = PLL0, HCLK = PLL0 / 2 */
         CLKCON = (CLKCON & ~0xFF00FF00) | 0x20003100;
         /* PCLK = HCLK / 2 */
@@ -235,6 +238,8 @@
         CLKCON2 &= ~0x200;
         /* FCLK_CPU = OFF, HCLK = PLL0 / 4 */
         CLKCON = (CLKCON & ~0xFF00FF00) | 0x80003300;
+        /* Configure for 50 MHz clock */
+        MIUSDPARA = 0x0061248D;
         /* Vcore = 0.900V */
         pmu_write(0x1e, 0xb);
     }