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Attached to Project: Rockbox
Opened by amiconn - 2005-11-02
Last edited by linusnielsen - 2005-11-19

FS#2733 - SDRAM init fixes

This patch fixes some (non-critical) problems with the
SDRAM init:

- Set RTIM = 00b (tRC = 3 clocks) for h100. 10b (tRC =
9 clocks) is a waste.
- Enable continous page mode
- Don’t perform extra wait between PALL and enabling
refresh - the required time is really short (20 ns)
- Wait between enabling refresh and mode register set
instead - the recommended timing is >= 8 refresh cycles
- No need to reset DACR0[IMRS], the SDRAM controller
resets it automatically

This patch touches bootloader code (only)! It should
not be tried without a BDM connected.

Closed by  linusnielsen
2005-11-19 01:27
Reason for closing:  Accepted

Info correction: RTIM was set to 01b for h100, which means
tRC = 6 clocks and is the correct value for > 92 MHz operation. For ⇐ 92 MHz it’s still a waste.


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