? cpufreq3.patch ? cpufreq4.patch ? h10 ? tools/codepages ? tools/rdf2binary Index: firmware/system.c =================================================================== RCS file: /cvsroot/rockbox/firmware/system.c,v retrieving revision 1.123 diff -u -r1.123 system.c --- firmware/system.c 8 Oct 2006 21:34:26 -0000 1.123 +++ firmware/system.c 24 Oct 2006 11:08:53 -0000 @@ -1275,49 +1275,149 @@ } #endif -/* Not all iPod targets support CPU freq. boosting yet */ #ifdef HAVE_ADJUSTABLE_CPU_FREQ void set_cpu_frequency(long frequency) { - unsigned long postmult; - - if (frequency == CPUFREQ_NORMAL) - postmult = CPUFREQ_NORMAL_MULT; - else if (frequency == CPUFREQ_MAX) - postmult = CPUFREQ_MAX_MULT; - else - postmult = CPUFREQ_DEFAULT_MULT; - cpu_frequency = frequency; - - /* Enable PLL? */ - outl(inl(0x70000020) | (1<<30), 0x70000020); - - /* Select 24MHz crystal as clock source? */ - outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020); - - /* Clock frequency = (24/8)*postmult */ - outl(0xaa020000 | 8 | (postmult << 8), 0x60006034); - - /* Wait for PLL relock? */ - udelay(2000); - - /* Select PLL as clock source? */ - outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020); - -#if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB) - /* We don't know why the timer interrupt gets disabled on the PP5020 - based ipods, but without the following line, the 4Gs will freeze - when CPU frequency changing is enabled. - - Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used - elsewhere to enable interrupts) doesn't work, we need "|=". - - It's not needed on the PP5021 and PP5022 ipods. - */ - - /* unmask interrupt source */ - CPU_INT_EN |= TIMER1_MASK; -#endif + if(cpu_frequency!=frequency){ + if (frequency == CPUFREQ_MAX) { + /* Check COP status bits 31 and 30 at COP_CTL */ + long cop_status = COP_CTL & ( (1<<31) | (1<<30) ); + + /* Set bits 27 and 31 in PLL_CONTROL reg */ + PLL_CONTROL |= ( (1<<27) | (1<<31) ); + + /* Disable IRQ and FIQ in CPSR */ + asm volatile("msr cpsr_c, #0xd3"); + + /* Write 0x40000000 to COP_CTL */ + COP_CTL = 0x40000000; + + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t"); + + /* Write 0x4800001f to CPU_CTL */ + CPU_CTL = 0x4800001f; + + /* Select 24MHz crystal as RUN source*/ + CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_24MHZ<<4); + + /* Write 0x4800000f to CPU_CTL */ + CPU_CTL = 0x4800000f; + + /* Execute three NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\t"); + + /* If COP status bits were zero */ + if(cop_status==0){ + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t"); + /* Write 0 to 0x60007004 */ + COP_CTL = 0; + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t"); + } + + /* Enable IRQ and FIQ in CPSR */ + asm volatile("msr cpsr_c, #0x13"); + + /* Set bits 0-15 of PLL_CONTROL for desired freq = (25/8)*24MHz */ + PLL_CONTROL = (PLL_CONTROL & 0xffff0000) | 8 | (25 << 8); + + /* Set bits 27 and 31 in PLL_CONTROL reg */ + PLL_CONTROL |= ( (1<<27) | (1<<31) ); + + /* If executing in COP */ + if(CURRENT_CORE == COP) + { + /* Write 0x420000c8 to 0x60007004; */ + COP_CTL = 0x420000c8; + } else { + /* Write 0x420000c8 to 0x60007000; */ + CPU_CTL = 0x420000c8; + } + + /* Disable IRQ and FIQ in CPSR */ + asm volatile("msr cpsr_c, #0xd3"); + + /* Write 0x40000000 to COP_CTL */ + COP_CTL = 0x40000000; + + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t"); + + /* Write 0x4800001f to CPU_CTL */ + CPU_CTL = 0x4800001f; + + /* Select PLL as RUN source*/ + CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_PLL<<4); + + /* Write 0x4800000f to CPU_CTL */ + CPU_CTL = 0x4800000f; + + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\t"); + + /* If COP status bits were zero */ + if(cop_status==0){ + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t"); + /* Write 0 to 0x60007004 */ + COP_CTL = 0; + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t"); + } + + /* Enable IRQ and FIQ in CPSR */ + asm volatile("msr cpsr_c, #0x13"); + + cpu_frequency = 75000000; + } else { + /* Check COP status bits 31 and 30 at COP_CTL */ + long cop_status = COP_CTL & ( (1<<31) | (1<<30) ); + + /* Set bit 27 in PLL_CONTROL reg */ + PLL_CONTROL |= (1<<27); + + /* Disable IRQ and FIQ in CPSR */ + asm volatile("msr cpsr_c, #0xd3"); + + /* Write 0x40000000 to COP_CTL */ + COP_CTL = 0x40000000; + + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t"); + + /* Write 0x4800001f to CPU_CTL */ + CPU_CTL = 0x4800001f; + + /* Select 24MHz crystal as RUN source */ + CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_24MHZ<<4); + + /* Write 0x4800000f to CPU_CTL */ + CPU_CTL = 0x4800000f; + + /* Execute three NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\t"); + + /* If COP status bits were zero */ + if(cop_status==0){ + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t"); + /* Write 0 to 0x60007004 */ + COP_CTL = 0; + /* Execute four NOPs */ + asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t"); + } + + /* Enable IRQ and FIQ in CPSR */ + asm volatile("msr cpsr_c, #0x13"); + + /* Clear bit 31 at PLL_CONTROL reg */ + PLL_CONTROL &=~ (1<<31); + + cpu_frequency = 24000000; + } + } } #elif !defined(BOOTLOADER) void ipod_set_cpu_frequency(void) @@ -1355,6 +1455,19 @@ outl(-1, 0x6000101c); #ifndef HAVE_ADJUSTABLE_CPU_FREQ ipod_set_cpu_frequency(); +#else + /* Enable PLL? */ + outl(inl(0x70000020) | (1<<30), 0x70000020); + + /* Select 24MHz crystal as clock source? */ + outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020); + + /* Clock frequency = (24/8)*postmult */ + outl(0xaa020000 | 8 | (25 << 8), 0x60006034); + + /* Wait for PLL relock? */ + udelay(2000); + #endif ipod_init_cache(); #endif Index: firmware/export/config-h10.h =================================================================== RCS file: /cvsroot/rockbox/firmware/export/config-h10.h,v retrieving revision 1.17 diff -u -r1.17 config-h10.h --- firmware/export/config-h10.h 2 Oct 2006 16:19:36 -0000 1.17 +++ firmware/export/config-h10.h 24 Oct 2006 11:08:53 -0000 @@ -137,7 +137,7 @@ #define CONFIG_LED LED_VIRTUAL /* Define this if you have adjustable CPU frequency */ -/*#define HAVE_ADJUSTABLE_CPU_FREQ*/ +#define HAVE_ADJUSTABLE_CPU_FREQ #define BOOTFILE_EXT "h10" #define BOOTFILE "rockbox." BOOTFILE_EXT Index: firmware/export/pp5020.h =================================================================== RCS file: /cvsroot/rockbox/firmware/export/pp5020.h,v retrieving revision 1.10 diff -u -r1.10 pp5020.h --- firmware/export/pp5020.h 20 Sep 2006 23:21:58 -0000 1.10 +++ firmware/export/pp5020.h 24 Oct 2006 11:08:53 -0000 @@ -122,11 +122,22 @@ #define GPIOK_INT_CLR (*(volatile unsigned long *)(0x6000d178)) #define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c)) -#define DEV_RS (*(volatile unsigned long *)(0x60006004)) -#define DEV_EN (*(volatile unsigned long *)(0x6000600c)) - +#define DEV_RS (*(volatile unsigned long *)(0x60006004)) +#define DEV_EN (*(volatile unsigned long *)(0x6000600c)) #define DEV_SYSTEM 0x4 +#define CLK_SRC (*(volatile unsigned long *)(0x60006020)) +#define CLK_SRC_32KHZ 0 +#define CLK_SRC_16MHZ 1 +#define CLK_SRC_24MHZ 2 +#define CLK_SRC_33MHZ 3 +#define CLK_SRC_48MHZ 4 +#define CLK_SRC_SLOW 5 /* 24MHz with additional divider */ +#define CLK_SRC_FAST 6 /* PLL with additional divider */ +#define CLK_SRC_PLL 7 + +#define PLL_CONTROL (*(volatile unsigned long *)(0x60006034)) + #define TIMER1_CFG (*(volatile unsigned long *)(0x60005000)) #define TIMER1_VAL (*(volatile unsigned long *)(0x60005004)) #define TIMER2_CFG (*(volatile unsigned long *)(0x60005008)) @@ -161,6 +172,9 @@ #define USB2D_IDENT (*(volatile unsigned long*)(0xc5000000)) #define USB_STATUS (*(volatile unsigned long*)(0xc50001a4)) +/* Bit 30 is PLL enable */ +#define DEVICE_CONTROL (*(volatile unsigned long*)(0x70000020)) + #define IISCONFIG (*(volatile unsigned long*)(0x70002800)) #define IISFIFO_CFG (*(volatile unsigned long*)(0x7000280c))