Index: firmware/system.c
===================================================================
RCS file: /cvsroot/rockbox/firmware/system.c,v
retrieving revision 1.124
diff -r1.124 system.c
1300d1299
< /* Not all iPod targets support CPU freq. boosting yet */
1304,1342c1303,1372
<     unsigned long postmult;
< 
<     if (frequency == CPUFREQ_NORMAL)
<         postmult = CPUFREQ_NORMAL_MULT;
<     else if (frequency == CPUFREQ_MAX)
<         postmult = CPUFREQ_MAX_MULT;
<     else
<         postmult = CPUFREQ_DEFAULT_MULT;
<     cpu_frequency = frequency;
< 
<     /* Enable PLL? */
<     outl(inl(0x70000020) | (1<<30), 0x70000020);
< 
<     /* Select 24MHz crystal as clock source? */
<     outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
< 
<     /* Clock frequency = (24/8)*postmult */
<     outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
< 
<     /* Wait for PLL relock? */
<     udelay(2000);
< 
<     /* Select PLL as clock source? */
<     outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
< 
< #if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
<     /* We don't know why the timer interrupt gets disabled on the PP5020
<        based ipods, but without the following line, the 4Gs will freeze
<        when CPU frequency changing is enabled.
< 
<        Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
<        elsewhere to enable interrupts) doesn't work, we need "|=".
< 
<        It's not needed on the PP5021 and PP5022 ipods.
<     */
< 
<     /* unmask interrupt source */
<     CPU_INT_EN |= TIMER1_MASK;
< #endif
---
>     if(cpu_frequency!=frequency){
>         if (frequency == CPUFREQ_MAX) {
>             /* Set bits 27 and 31 in PLL_CONTROL reg */
>             PLL_CONTROL |= ( (1<<27) | (1<<31) );
>            
>             /* Disable IRQ and FIQ in CPSR */
>             asm volatile("msr    cpsr_c, #0xd3");
>             
>             /* Execute four NOPs */
>             asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
>     
>             /* Select 24MHz crystal as RUN source*/
>             CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_24MHZ<<4);
>             
>             /* Execute three NOPs */
>             asm volatile("nop\n\tnop\n\tnop\n\t");
>     
>             /* Enable IRQ and FIQ in CPSR */
>             asm volatile("msr    cpsr_c, #0x13");
>             
>             /* Set bits 0-15 of PLL_CONTROL for desired freq = (25/8)*24MHz */
>             PLL_CONTROL = (PLL_CONTROL & 0xffff0000) | 8 | (25 << 8);
>     
>             /* Set bits 27 and 31 in PLL_CONTROL reg */
>             PLL_CONTROL |= ( (1<<27) | (1<<31) );
>             
>             /* Disable IRQ and FIQ in CPSR */
>             asm volatile("msr    cpsr_c, #0xd3");
>     
>             /* Write 0x40000000 to COP_CTL */
>             COP_CTL = 0x40000000;
>     
>             /* Execute four NOPs */
>             asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
>             
>             /* Select PLL as RUN source*/
>             CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_PLL<<4);
>             
>             /* Execute four NOPs */
>             asm volatile("nop\n\tnop\n\tnop\n\t");
>     
>             /* Enable IRQ and FIQ in CPSR */
>             asm volatile("msr    cpsr_c, #0x13");
>             
>             cpu_frequency = 75000000;
>         } else {
>             /* Set bit 27 in PLL_CONTROL reg */
>             PLL_CONTROL |= (1<<27);
>             
>             /* Disable IRQ and FIQ in CPSR */
>             asm volatile("msr    cpsr_c, #0xd3");
>             
>             /* Execute four NOPs */
>             asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
>     
>             /* Select 24MHz crystal as RUN source */
>             CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_24MHZ<<4);
>             
>             /* Execute three NOPs */
>             asm volatile("nop\n\tnop\n\tnop\n\t");
>     
>             /* Enable IRQ and FIQ in CPSR */
>             asm volatile("msr    cpsr_c, #0x13");
>             
>             /* Clear bit 31 at PLL_CONTROL reg */
>             PLL_CONTROL &=~ (1<<31);
>     
>             cpu_frequency = 24000000;
>         }
>     }
1379a1410,1422
> #else
>     /* Enable PLL? */
>     outl(inl(0x70000020) | (1<<30), 0x70000020);
> 
>     /* Select 24MHz crystal as clock source? */
>     outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
> 
>     /* Clock frequency = (24/8)*postmult */
>     outl(0xaa020000 | 8 | (25 << 8), 0x60006034);
> 
>     /* Wait for PLL relock? */
>     udelay(2000);
> 
Index: firmware/export/config-h10.h
===================================================================
RCS file: /cvsroot/rockbox/firmware/export/config-h10.h,v
retrieving revision 1.18
diff -r1.18 config-h10.h
142c142
< /*#define HAVE_ADJUSTABLE_CPU_FREQ*/
---
> #define HAVE_ADJUSTABLE_CPU_FREQ
Index: firmware/export/pp5020.h
===================================================================
RCS file: /cvsroot/rockbox/firmware/export/pp5020.h,v
retrieving revision 1.10
diff -r1.10 pp5020.h
125,127c125,126
< #define DEV_RS (*(volatile unsigned long *)(0x60006004))
< #define DEV_EN (*(volatile unsigned long *)(0x6000600c))
< 
---
> #define DEV_RS              (*(volatile unsigned long *)(0x60006004))
> #define DEV_EN              (*(volatile unsigned long *)(0x6000600c))
129a129,140
> #define CLK_SRC          (*(volatile unsigned long *)(0x60006020))
> #define CLK_SRC_32KHZ    0
> #define CLK_SRC_16MHZ    1
> #define CLK_SRC_24MHZ    2
> #define CLK_SRC_33MHZ    3
> #define CLK_SRC_48MHZ    4
> #define CLK_SRC_SLOW     5   /* 24MHz with additional divider */
> #define CLK_SRC_FAST     6   /* PLL with additional divider */
> #define CLK_SRC_PLL      7
> 
> #define PLL_CONTROL     (*(volatile unsigned long *)(0x60006034))
> 
163a175,177
> /* Bit 30 is PLL enable */
> #define DEVICE_CONTROL      (*(volatile unsigned long*)(0x70000020))
>