Index: firmware/target/arm/system-pp502x.c
===================================================================
--- firmware/target/arm/system-pp502x.c	(revision 15632)
+++ firmware/target/arm/system-pp502x.c	(working copy)
@@ -182,6 +182,7 @@
         MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
 #endif
 #if CONFIG_CPU == PP5020
+        IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */
         PLL_CONTROL  = 0x8a020a03;  /* 10/3 * 24MHz */
         PLL_STATUS   = 0xd19b;      /* unlock frequencies > 66MHz */
         PLL_CONTROL  = 0x8a020a03;  /* repeat setup */
@@ -207,6 +208,7 @@
         scale_suspend_core(false);
         udelay(500);                /* wait for relock */
 #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
+        IDE0_CFG |= (0x10000000); /* Set CPU > 65MHz bit */
         PLL_CONTROL  = 0x8a220501;  /* (5/1 * 24MHz) / 4 */
         scale_suspend_core(false);
         udelay(250);