Index: firmware/target/arm/system-pp502x.c
===================================================================
--- firmware/target/arm/system-pp502x.c	(revision 15632)
+++ firmware/target/arm/system-pp502x.c	(working copy)
@@ -178,6 +178,7 @@
       case CPUFREQ_MAX:
         CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
         DEV_TIMING1  = 0x00000303;
+        IDE0_CFG |= (0x10000000); /* Set CPU > 65MHz bit */
 #ifdef IPOD_MINI2G
         MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
 #endif
@@ -199,6 +200,7 @@
       case CPUFREQ_NORMAL:
         CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
         DEV_TIMING1  = 0x00000303;
+        IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */
 #ifdef IPOD_MINI2G
         MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
 #endif
@@ -229,6 +231,7 @@
 #ifdef IPOD_MINI2G
         MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
 #endif
+        IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */
         PLL_CONTROL &= ~0x80000000; /* disable PLL */
         cpu_frequency = CPUFREQ_DEFAULT;
         PROC_CTL(CURRENT_CORE) = 0x4800001f; nop;