diff --git a/firmware/target/arm/ata-pp5020.c b/firmware/target/arm/ata-pp5020.c
index 022d165..2a64e64 100644
--- a/firmware/target/arm/ata-pp5020.c
+++ b/firmware/target/arm/ata-pp5020.c
@@ -44,7 +44,7 @@ void ata_device_init()
 {
     /* From ipod-ide.c:ipod_ide_register() */
     IDE0_CFG |= (1<<5);
-    IDE0_CFG &=~(0x10000000);   /* cpu < 65MHz */
+    IDE0_CFG |= (0x10000000); /* cpu > 65MHz */
 
     IDE0_PRI_TIMING0 = 0x10;
     IDE0_PRI_TIMING1 = 0x80002150;
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index a1c4d16..2fa59d1 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -178,6 +178,7 @@ static void pp_set_cpu_frequency(long frequency)
       case CPUFREQ_MAX:
         CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
         DEV_TIMING1  = 0x00000303;
+	IDE0_CFG |= (0x10000000); /* Set CPU > 65MHz bit */
 #ifdef IPOD_MINI2G
         MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
 #endif
@@ -199,6 +200,7 @@ static void pp_set_cpu_frequency(long frequency)
       case CPUFREQ_NORMAL:
         CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
         DEV_TIMING1  = 0x00000303;
+	IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */
 #ifdef IPOD_MINI2G
         MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
 #endif
@@ -229,6 +231,7 @@ static void pp_set_cpu_frequency(long frequency)
 #ifdef IPOD_MINI2G
         MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
 #endif
+	IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */
         PLL_CONTROL &= ~0x80000000; /* disable PLL */
         cpu_frequency = CPUFREQ_DEFAULT;
         PROC_CTL(CURRENT_CORE) = 0x4800001f; nop;