Index: firmware/drivers/usb/arcotg_dcd.c =================================================================== --- firmware/drivers/usb/arcotg_dcd.c (revision 15673) +++ firmware/drivers/usb/arcotg_dcd.c (working copy) @@ -147,8 +147,8 @@ ep_num++; } - logf("pipe %d -> ep %d %s", dcd_controller.endpoints[i].pipe_num, - dcd_controller.endpoints[i].ep_num, + logf("pipe %d -> ep %d %s", (int) dcd_controller.endpoints[i].pipe_num, + (int) dcd_controller.endpoints[i].ep_num, dcd_controller.endpoints[i].name); if (ep_name[i] != NULL) { @@ -416,6 +416,7 @@ uint32_t bit_pos; int i, ep_num, direction, bit_mask /*, status*/; + struct usb_ep *ep; /* clear the bits in the register */ bit_pos = UDC_ENDPTCOMPLETE; @@ -437,7 +438,13 @@ logf(" "); logf("TRAFFIC"); - logf(" -> on ep %d dir %d", i, direction); + logf(" -> on ep %d dir %d", i >> 1, direction); /* SXT */ + if (ep_num > 0) { + ep = &dcd_controller.endpoints[i]; + if (ep != NULL && ep->command != NULL) { + ep->command(ep, buffer); + } + } } } @@ -490,7 +497,34 @@ /*-------------------------------------------------------------------------*/ /* usb controller ops */ +void activate_receive(struct usb_ep* ep) +{ + int index; + int retval = 0; + struct dtd* td; + struct dqh* qh; + unsigned int mask; + index = ep->pipe_num; + + td = &dev_td[index]; + qh = &dev_qh[index]; + if ((index % 2) != 0) { + mask = 1 << (16 + ep->ep_num); + } else { + mask = 1 << ep->ep_num; + } + + /* init transfer descritpor */ + td_init(td, buffer, BUFFER_SIZE); + + qh->dtd_ovrl.next_dtd = (unsigned int)td; + qh->dtd_ovrl.dtd_token &= ~0xc0; + /* start transfer */ + retval = td_enqueue(td, qh, mask); + +} + int usb_arcotg_dcd_enable(struct usb_ep* ep, struct usb_endpoint_descriptor* desc) { @@ -633,14 +667,13 @@ /* Init EPx Queue Head (Ep Capabilites field in QH * according to max, zlt, mult) */ qh_init(ep->ep_num, - (desc->bEndpointAddress & USB_DIR_IN) ? USB_RECV : USB_SEND, + (ep->pipe_num % 2) ? USB_SEND : USB_RECV, (unsigned char) (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK), max, zlt, mult); /* Init endpoint x at here */ ep_setup(ep->ep_num, - (unsigned char)(desc->bEndpointAddress & USB_DIR_IN) ? - USB_RECV : USB_SEND, + (ep->pipe_num % 2) ? USB_SEND : USB_RECV, (unsigned char)(desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)); /* Now HW will be NAKing transfers to that EP, @@ -669,6 +702,8 @@ (desc->bEndpointAddress & USB_DIR_IN) ? "in" : "out", val); logf(" maxpacket %d", max); + if ((ep->pipe_num % 2) == 0) + activate_receive(ep); en_done: return retval; } @@ -755,6 +790,9 @@ if (ep != NULL) { index = ep->pipe_num; + mask = 1 << (16 + ep->ep_num); + } else { + mask = 1 << 16; } ptr = res->buf; @@ -762,7 +800,6 @@ td = &dev_td[index]; qh = &dev_qh[index]; - mask = 1 << (15 + index); do { /* calculate how much to copy and send */ @@ -805,14 +842,24 @@ struct dtd* td; struct dqh* qh; unsigned int mask; + int i; if (res == NULL) { - logf("invalid input"); - return -EINVAL; + if (ep != NULL) + { + activate_receive(ep); + return 0; + } else { + logf("invalid input"); + return -EINVAL; + } } if (ep != NULL) { index = ep->pipe_num; + mask = 1 << ep->ep_num; + } else { + mask = 1 << index; } ptr = res->buf; @@ -820,7 +867,6 @@ td = &dev_td[index]; qh = &dev_qh[index]; - mask = 1 << index; do { /* calculate how much to receive in one step */ @@ -940,14 +986,14 @@ if (ep_num) { tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; } - logf("tx enablde"); + logf("tx enabled"); tmp_epctrl |= EPCTRL_TX_ENABLE; tmp_epctrl |= ((unsigned int)(ep_type) << EPCTRL_TX_EP_TYPE_SHIFT); } else { if (ep_num) { tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; } - logf("rx enablde"); + logf("rx enabled"); tmp_epctrl |= EPCTRL_RX_ENABLE; tmp_epctrl |= ((unsigned int)(ep_type) << EPCTRL_RX_EP_TYPE_SHIFT); }