Index: firmware/export/powermgmt.h =================================================================== --- firmware/export/powermgmt.h (revision 15980) +++ firmware/export/powermgmt.h (working copy) @@ -111,7 +111,7 @@ # define CURRENT_RECORD 35 /* FIXME: this needs adjusting */ #endif #elif defined(IPOD_VIDEO) /* iPOD Video */ -# define CURRENT_NORMAL 42 /* 9.5h out of 400mAh battery (30GB) or 14h out of 600mAh (60GB) from IpodRuntime */ +# define CURRENT_NORMAL 36 /* 11h out of 400mAh battery (30GB) or 16h out of 600mAh (60GB) from IpodRuntime */ # define CURRENT_BACKLIGHT 20 /* FIXME: this needs adjusting */ #if defined(HAVE_RECORDING) # define CURRENT_RECORD 35 /* FIXME: this needs adjusting */ Index: firmware/export/pp5020.h =================================================================== --- firmware/export/pp5020.h (revision 15980) +++ firmware/export/pp5020.h (working copy) @@ -133,6 +133,7 @@ #define DEV_EN2 (*(volatile unsigned long *)(0x60006010)) #define DEV_SYSTEM 0x00000004 +#define DEV_USB0 0x00000008 #define DEV_SER0 0x00000040 #define DEV_SER1 0x00000080 #define DEV_I2S 0x00000800 @@ -140,7 +141,7 @@ #define DEV_ATA 0x00004000 #define DEV_OPTO 0x00010000 #define DEV_PIEZO 0x00010000 -#define DEV_USB 0x00400000 +#define DEV_USB1 0x00400000 #define DEV_FIREWIRE 0x00800000 #define DEV_IDE0 0x02000000 #define DEV_LCD 0x04000000 @@ -332,6 +333,8 @@ #define XMB_NOR_CFG (*(volatile unsigned long *)(0x70000038)) #define XMB_RAM_CFG (*(volatile unsigned long *)(0x7000003c)) +#define INIT_BUTTONS 0x00040000 +#define INIT_PLL 0x40000000 #define INIT_USB 0x80000000 /* 32 bit GPO port */ Index: firmware/target/arm/usb-fw-pp502x.c =================================================================== --- firmware/target/arm/usb-fw-pp502x.c (revision 15980) +++ firmware/target/arm/usb-fw-pp502x.c (working copy) @@ -33,18 +33,23 @@ void usb_init_device(void) { /* enable usb module */ - GPO32_ENABLE |= 0x200; - outl(inl(0x7000002C) | 0x3000000, 0x7000002C); - DEV_EN |= DEV_USB; + DEV_EN |= DEV_USB0; + DEV_EN |= DEV_USB1; - DEV_RS |= DEV_USB; /* reset usb start */ - DEV_RS &=~DEV_USB;/* reset usb end */ + /* reset both USBs */ +// DEV_RS |= DEV_USB0; +// DEV_RS &=~DEV_USB0; + DEV_RS |= DEV_USB1; + DEV_RS &=~DEV_USB1; - DEV_INIT2 |= INIT_USB; while ((inl(0x70000028) & 0x80) == 0); outl(inl(0x70000028) | 0x2, 0x70000028); udelay(0x186A0); + + /* disable USB-devices until USB is detected via GPIO */ + DEV_EN &= ~DEV_USB0; + DEV_EN &= ~DEV_USB1; #if defined(IPOD_COLOR) || defined(IPOD_4G) \ || defined(IPOD_MINI) || defined(IPOD_MINI2G) @@ -85,33 +90,43 @@ static bool usb_pin_detect(void) { + bool retval = false; + #if defined(IPOD_4G) || defined(IPOD_COLOR) \ || defined(IPOD_MINI) || defined(IPOD_MINI2G) /* GPIO D bit 3 is usb detect */ if (GPIOD_INPUT_VAL & 0x08) - return true; + retval = true; #elif defined(IPOD_NANO) || defined(IPOD_VIDEO) /* GPIO L bit 4 is usb detect */ if (GPIOL_INPUT_VAL & 0x10) - return true; + retval = true; #elif defined(SANSA_C200) /* GPIO H bit 1 is usb detect */ if (GPIOH_INPUT_VAL & 0x02) - return true; + retval = true; #elif defined(SANSA_E200) /* GPIO B bit 4 is usb detect */ if (GPIOB_INPUT_VAL & 0x10) - return true; + retval = true; #elif defined(IRIVER_H10) || defined(IRIVER_H10_5GB) /* GPIO L bit 2 is usb detect */ if (GPIOL_INPUT_VAL & 0x4) - return true; + retval = true; #endif - return false; + + /* if USB is detected, re-enable the USB-devices */ + if (retval) + { + DEV_EN |= DEV_USB0; + DEV_EN |= DEV_USB1; + } + + return retval; } /* detect host or charger (INSERTED or POWERED) */ Index: firmware/target/arm/ipod/button-clickwheel.c =================================================================== --- firmware/target/arm/ipod/button-clickwheel.c (revision 15980) +++ firmware/target/arm/ipod/button-clickwheel.c (working copy) @@ -73,64 +73,40 @@ static void opto_i2c_init(void) { - int i, curr_value; - - /* wait for value to settle */ - i = 1000; - curr_value = (inl(0x7000c104) << 16) >> 24; - while (i > 0) - { - int new_value = (inl(0x7000c104) << 16) >> 24; - - if (new_value != curr_value) { - i = 10000; - curr_value = new_value; - } - else { - i--; - } - } - - GPIOB_OUTPUT_VAL |= 0x10; - DEV_EN |= 0x10000; - DEV_RS |= 0x10000; + DEV_EN |= DEV_OPTO; + DEV_RS |= DEV_OPTO; udelay(5); - DEV_RS &= ~0x10000; /* finish reset */ + DEV_RS &= ~DEV_OPTO; /* finish reset */ + DEV_INIT1 |= INIT_BUTTONS; /* enable buttons (needed for "hold"-detection) */ - outl(0xffffffff, 0x7000c120); - outl(0xffffffff, 0x7000c124); outl(0xc00a1f00, 0x7000c100); - outl(0x1000000, 0x7000c104); + outl(0x01000000, 0x7000c104); } static inline int ipod_4g_button_read(void) { int whl = -1; + int btn = BUTTON_NONE; - /* The ipodlinux source had a udelay(250) here, but testing has shown that - it is not needed - tested on Nano, Color/Photo and Video. */ - /* udelay(250);*/ + /* The following delay was 250 in the ipodlinux source, but 50 seems to + work fine - tested on Nano, Color/Photo and Video. */ + udelay(50); - int btn = BUTTON_NONE; - unsigned reg = 0x7000c104; - if ((inl(0x7000c104) & 0x4000000) != 0) + if ((inl(0x7000c104) & 0x04000000) != 0) { unsigned status = inl(0x7000c140); - reg = reg + 0x3C; /* 0x7000c140 */ - outl(0x0, 0x7000c140); /* clear interrupt status? */ - if ((status & 0x800000ff) == 0x8000001a) { - if (status & 0x100) + if (status & 0x00000100) btn |= BUTTON_SELECT; - if (status & 0x200) + if (status & 0x00000200) btn |= BUTTON_RIGHT; - if (status & 0x400) + if (status & 0x00000400) btn |= BUTTON_LEFT; - if (status & 0x800) + if (status & 0x00000800) btn |= BUTTON_PLAY; - if (status & 0x1000) + if (status & 0x00001000) btn |= BUTTON_MENU; if (status & 0x40000000) { @@ -263,19 +239,10 @@ } } - else if (status == 0xffffffff) - { - opto_i2c_init(); - } } - if ((inl(reg) & 0x8000000) != 0) - { - outl(0xffffffff, 0x7000c120); - outl(0xffffffff, 0x7000c124); - } - /* Save the new absolute wheel position */ #ifdef HAVE_WHEEL_POSITION + /* Save the new absolute wheel position */ wheel_position = whl; #endif return btn; @@ -296,16 +263,12 @@ void ipod_4g_button_int(void) { CPU_HI_INT_CLR = I2C_MASK; - /* The following delay was 250 in the ipodlinux source, but 50 seems to - work fine - tested on Nano, Color/Photo and Video. */ - udelay(50); - outl(0x0, 0x7000c140); + int_btn = ipod_4g_button_read(); - outl(inl(0x7000c104) | 0xC000000, 0x7000c104); + + outl(inl(0x7000c104) | 0x0c000000, 0x7000c104); outl(0x400a1f00, 0x7000c100); - GPIOB_OUTPUT_VAL |= 0x10; - CPU_INT_EN = 0x40000000; CPU_HI_INT_EN = I2C_MASK; } @@ -317,15 +280,8 @@ GPIOA_ENABLE |= 0x20; GPIOA_OUTPUT_EN &= ~0x20; - /* hold button - set interrupt levels */ - GPIOA_INT_LEV = ~(GPIOA_INPUT_VAL & 0x20); - GPIOA_INT_CLR = GPIOA_INT_STAT & 0x20; - - /* enable interrupts */ - GPIOA_INT_EN = 0x20; - /* unmask interrupt */ - CPU_INT_EN = 0x40000000; + CPU_INT_EN = HI_MASK; CPU_HI_INT_EN = I2C_MASK; } @@ -342,7 +298,20 @@ hold_button = button_hold(); if (hold_button != hold_button_old) + { backlight_hold_changed(hold_button); + + if (hold_button) + { + /* lock -> disable wheel sensor */ + DEV_EN &= ~DEV_OPTO; + } + else + { + /* unlock -> enable wheel sensor */ + DEV_EN |= DEV_OPTO; + } + } /* The int_btn variable is set in the button interrupt handler */ return int_btn; Index: firmware/target/arm/ipod/power-ipod.c =================================================================== --- firmware/target/arm/ipod/power-ipod.c (revision 15980) +++ firmware/target/arm/ipod/power-ipod.c (working copy) @@ -71,9 +71,15 @@ GPIO_SET_BITWISE(GPIOJ_OUTPUT_VAL, 0x04); #elif defined(IPOD_VIDEO) if (on) + { GPO32_VAL &= ~0x40000000; + DEV_EN |= DEV_IDE0; + } else + { + DEV_EN &= ~DEV_IDE0; GPO32_VAL |= 0x40000000; + } #else /* Nano */ (void)on; /* Do nothing. */ #endif Index: firmware/target/arm/system-pp502x.c =================================================================== --- firmware/target/arm/system-pp502x.c (revision 15980) +++ firmware/target/arm/system-pp502x.c (working copy) @@ -177,10 +177,11 @@ * PP5026 is similar to PP5022 except it doesn't * have this limitation (and the post divider?) */ case CPUFREQ_MAX: + DEV_INIT2 |= INIT_PLL; /* enable PLL power */ CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ DEV_TIMING1 = 0x00000303; #ifdef IPOD_NANO - IDE0_CFG |= (0x10000000); /* Set CPU > 65MHz bit */ + IDE0_CFG |= (0x10000000); /* set ">65MHz" bit */ #endif #ifdef IPOD_MINI2G MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */ @@ -192,7 +193,8 @@ scale_suspend_core(false); udelay(500); /* wait for relock */ #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) - PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */ + PLL_CONTROL = 0x8a121403; /* 80 MHz = (20/3 * 24MHz) / 2 */ + //PLL_CONTROL = 0x8a121903; /* 100 MHz = (25/3 * 24MHz) / 2 */ scale_suspend_core(false); udelay(250); while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ @@ -201,10 +203,13 @@ break; case CPUFREQ_NORMAL: +#if 1 + //-------------- svn with PLL ---------------- + DEV_INIT2 |= INIT_PLL; /* enable PLL power */ CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ DEV_TIMING1 = 0x00000303; #ifdef IPOD_NANO - IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */ + IDE0_CFG &=~(0x10000000); /* clear ">65MHz" bit */ #endif #ifdef IPOD_MINI2G MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ @@ -214,17 +219,38 @@ scale_suspend_core(false); udelay(500); /* wait for relock */ #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) - PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */ + PLL_CONTROL = 0x8a220501; /* 30 MHz = (5/1 * 24MHz) / 4 */ + //PLL_CONTROL = 0x8a220401; /* 24 MHz = (4/1 * 24MHz) / 4 */ scale_suspend_core(false); udelay(250); while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ #endif scale_suspend_core(true); break; + //-------------- svn with PLL ---------------- +#else + //-------------- new without PLL ---------------- + CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ + DEV_TIMING1 = 0x00000303; +#ifdef IPOD_MINI2G + MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ +#endif +#ifdef IPOD_NANO + IDE0_CFG &=~(0x10000000); /* clear ">65MHz" bit */ +#endif + PLL_CONTROL &= ~0x80000000; /* disable PLL */ + DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ + scale_suspend_core(false); + udelay(10000); + scale_suspend_core(true); + break; + //-------------- new without PLL ---------------- +#endif case CPUFREQ_SLEEP: CLOCK_SOURCE = 0x10002202; /* source #2: 32kHz, #1, #3, #4: 24MHz */ PLL_CONTROL &= ~0x80000000; /* disable PLL */ + DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ scale_suspend_core(false); udelay(10000); /* let 32kHz source stabilize? */ scale_suspend_core(true); @@ -237,9 +263,10 @@ MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ #endif #ifdef IPOD_NANO - IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */ + IDE0_CFG &=~(0x10000000); /* clear ">65MHz" bit */ #endif PLL_CONTROL &= ~0x80000000; /* disable PLL */ + DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ cpu_frequency = CPUFREQ_DEFAULT; PROC_CTL(CURRENT_CORE) = 0x4800001f; nop; break; @@ -276,6 +303,28 @@ outl(inl(0x70000024) | 0xc0, 0x70000024); DEV_RS = 0; DEV_RS2 = 0; +#elif defined (IPOD_VIDEO) + //DEV_EN = 0xc2c1197f; /* DEV_EN1 by default */ + //DEV_EN2 = 0x00000000; /* DEV_EN2 by default */ + //CACHE_PRIORITY = 0x0007003f; /* DEV_EN3 by default */ + //GPO32_ENABLE = 0xfe80feff; /* GPO32_EN by default */ + //GPO32_VAL = 0x00804000; /* GPO32_VAL by default */ + //DEV_INIT1 = 0x00040000; /* INIT1 by default */ + //DEV_INIT2 = 0x40000000; /* INIT2 by default 0x40000000 = PLL, need for boot */ + + DEV_EN = 0xc2011926; /* DEV_EN1 from own tests */ + DEV_EN2 = 0x00000000; /* DEV_EN2 same as svn */ + CACHE_PRIORITY = 0x0000003f; /* DEV_EN3 from own tests */ + GPO32_ENABLE = 0x40004000; /* GPO32_EN from own tests */ + GPO32_VAL = 0x00004000; /* GPO32_VAL from own tests */ + DEV_INIT1 = 0x00000000; /* INIT1 from own tests */ +// DEV_INIT2 = 0x40000000; /* INIT2 same as svn */ + + /* reset all allowed devices */ + DEV_RS = 0x3ffffef8; + DEV_RS2 = 0xffffffff; + DEV_RS = 0x00000000; + DEV_RS2 = 0x00000000; #endif #if !defined(SANSA_E200) && !defined(SANSA_C200) @@ -314,7 +363,7 @@ outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */ #endif - DEV_INIT2 |= 1 << 30; /* enable PLL power */ +//AB DEV_INIT2 |= INIT_PLL; /* enable PLL power */ #ifdef HAVE_ADJUSTABLE_CPU_FREQ #if NUM_CORES > 1