==== Patch <as352x> level 1
Source: 8f6a5c09-68cf-4266-a87f-52910e4d178a:/local/rockbox/trunk:17004 [local]
Target: a1c6a512-1295-4272-9138-f99709370657:/trunk:16933 [mirrored]
        (svn://svn.rockbox.org/rockbox)
Log:
- as352x patch against latest rockbox revision
=== tools/configure
==================================================================
--- tools/configure	(revision 16933)
+++ tools/configure	(patch as352x level 1)
@@ -620,7 +620,7 @@
  30) X5/X5V/X5L        40) Gigabeat F         50) Sansa e200
  31) M5/M5L            41) Gigabeat S         51) Sansa e200R
  32) 7                                        52) Sansa c200
- 33) Cowon D2
+ 33) Cowon D2                                 53) Sansa e200(v2)
  34) M3/M3L
 
  ==Tatung==            ==Olympus==            ==Logik==
@@ -1497,6 +1497,33 @@
     t_model="sansa-c200"
     ;;
 
+   53|e200v2)
+    target_id=23
+    modelname="e200v2"
+    target="-DSANSA_E200_V2"
+    memory=8 # supposedly
+    arm9tdmicc
+    tool="$rootdir/tools/scramble -mi4v3 -model=e200 -type=RBOS"
+    #tool="cp "
+    bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
+    bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
+    output="rockbox.bin"
+    appextra="recorder:gui"
+    plugins="yes"
+    swcodec="yes"
+    boottool="$rootdir/tools/scramble -mi4v3 -model=e200 -type=RBBL"
+    #boottool="cp "
+    bootoutput="e200boot.bin"
+    # toolset is the tools within the tools directory that we build for
+    # this particular target.
+    toolset="$genericbitmaptools scramble"
+    # architecture, manufacturer and model for the target-tree build
+    t_cpu="arm"
+    t_manufacturer="sandisk"
+    t_model="sansa-e200" # we can change target later if needed
+    ;;
+
+
    60|tpj1022)
     target_id=25
     modelname="tpj1022"
=== bootloader/SOURCES
==================================================================
--- bootloader/SOURCES	(revision 16933)
+++ bootloader/SOURCES	(patch as352x level 1)
@@ -27,4 +27,6 @@
 mrobe500.c
 #elif defined(CPU_TCC77X) || defined(CPU_TCC780X)
 telechips.c
+#elif defined(CPU_AS352X)
+as352x.c
 #endif
=== bootloader/as352x.c
==================================================================
--- bootloader/as352x.c	(revision 16933)
+++ bootloader/as352x.c	(patch as352x level 1)
@@ -0,0 +1,131 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Greg White
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "inttypes.h"
+#include "string.h"
+#include "cpu.h"
+#include "system.h"
+#include "lcd.h"
+#include "kernel.h"
+#include "thread.h"
+#include "ata.h"
+#include "fat.h"
+#include "disk.h"
+#include "font.h"
+#include "adc.h"
+#include "backlight.h"
+#include "backlight-target.h"
+#include "button.h"
+#include "panic.h"
+#include "power.h"
+#include "file.h"
+#include "common.h"
+#include "rbunicode.h"
+#include "usb.h"
+#include "mmu-arm.h"
+
+#include <stdarg.h>
+
+char version[] = APPSVERSION;
+
+void main(void)
+{
+    unsigned char* loadbuffer;
+    int buffer_size;
+    int rc;
+    int(*kernel_entry)(void);
+
+    memory_init();
+    power_init();
+    system_init();
+    lcd_init();
+    backlight_init();
+    font_init();
+
+    lcd_setfont(FONT_SYSFIXED);
+
+    usb_init();
+
+    /* Enter USB mode without USB thread */
+    if(usb_detect() == USB_INSERTED)
+    {
+        const char msg[] = "Bootloader USB mode";
+        reset_screen();
+        lcd_putsxy( (LCD_WIDTH - (SYSFONT_WIDTH * strlen(msg))) / 2,
+                    (LCD_HEIGHT - SYSFONT_HEIGHT) / 2, msg);
+        lcd_update();
+
+        ata_enable(false);
+        sleep(HZ/20);
+        usb_enable(true);
+
+        while (usb_detect() == USB_INSERTED)
+            sleep(HZ);
+
+        usb_enable(false);
+
+        reset_screen();
+        lcd_update();
+    }
+    
+    kernel_init();
+    adc_init();
+    button_init();
+
+    /* Show debug messages if button is pressed */
+    if(button_read_device())
+        verbose = true;
+
+    printf("Rockbox boot loader");
+    printf("Version %s", version);
+
+    rc = ata_init();
+    if(rc)
+    {
+        reset_screen();
+        error(EATA, rc);
+    }
+
+    disk_init();
+
+    rc = disk_mount_all();
+    if (rc<=0)
+    {
+        error(EDISK,rc);
+    }
+
+    printf("Loading firmware");
+
+    loadbuffer = (unsigned char*) 0x100;
+    buffer_size = (unsigned char*)0x400000 - loadbuffer;
+
+    rc = load_firmware(loadbuffer, BOOTFILE, buffer_size);
+    if(rc < 0)
+        error(EBOOTFILE, rc);
+
+    if (rc == EOK)
+    {
+        kernel_entry = (void*) loadbuffer;
+        rc = kernel_entry();
+    }
+}
+

Property changes on: bootloader/as352x.c
___________________________________________________________________
Name: svn:eol-style
 +native
Name: svn:keywords
 +"HeadURL Id LastChangedBy LastChangedDate LastChangedRevision"
Name: svn:mime-type
 +text/x-csrc

=== firmware/export/config-e200v2.h
==================================================================
--- firmware/export/config-e200v2.h	(revision 16933)
+++ firmware/export/config-e200v2.h	(patch as352x level 1)
@@ -0,0 +1,204 @@
+/*
+ * This config file is for the Sandisk Sansa e200 v2
+ *
+ * Taken from config_e200.h,
+ *
+ * so check *any* definition here
+ */
+#define TARGET_TREE /* this target is using the target tree system */
+
+/* For Rolo and boot loader */
+#define MODEL_NUMBER 16 /* TODO: Check wether we need a new model no.*/
+#define MODEL_NAME   "Sandisk Sansa e200 v2"
+
+#define HW_SAMPR_CAPS       (SAMPR_CAP_44)
+
+/* define this if you have recording possibility */
+#define HAVE_RECORDING
+
+#define REC_SAMPR_CAPS      (SAMPR_CAP_22)
+#define REC_FREQ_DEFAULT    REC_FREQ_22 /* Default is not 44.1kHz */
+#define REC_SAMPR_DEFAULT   SAMPR_22
+
+/* Define bitmask of input sources - recordable bitmask can be defined
+   explicitly if different */
+#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_FMRADIO)
+
+/* define this if you have a bitmap LCD display */
+#define HAVE_LCD_BITMAP
+
+/* define this if you have a colour LCD */
+#define HAVE_LCD_COLOR
+
+/* define this if you want album art for this target */
+#define HAVE_ALBUMART
+
+/* define this if you have a light associated with the buttons */
+#define HAVE_BUTTON_LIGHT
+
+/* define this if you have access to the quickscreen */
+#define HAVE_QUICKSCREEN
+
+/* define this if you have access to the pitchscreen */
+#define HAVE_PITCHSCREEN
+
+/* define this if you would like tagcache to build on this target */
+#define HAVE_TAGCACHE
+
+/* LCD dimensions */
+#define LCD_WIDTH  176
+#define LCD_HEIGHT 220
+#define LCD_DEPTH  16   /* 65536 colours */
+#define LCD_PIXELFORMAT RGB565 /* rgb565 */
+
+/* define this if you have LCD enable function */
+#define HAVE_LCD_ENABLE
+
+/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
+   should be defined as well. */
+#define HAVE_LCD_SLEEP
+
+/* define this if you can flip your LCD */
+#define HAVE_LCD_FLIP
+
+/* define this if you can invert the colours on your LCD */
+#define HAVE_LCD_INVERT
+
+/* #define IRAM_LCDFRAMEBUFFER IDATA_ATTR *//* put the lcd frame buffer in IRAM */
+
+#define CONFIG_KEYPAD SANSA_E200_PAD
+
+/* Define this if you do software codec */
+#define CONFIG_CODEC SWCODEC
+/* There is no hardware tone control */
+#define HAVE_SW_TONE_CONTROLS
+/* The PP5024 has a built-in AustriaMicrosystems AS3514 */
+#define HAVE_AS3514
+
+/* define this if you have a real-time clock */
+#ifndef BOOTLOADER
+#define CONFIG_RTC RTC_AS3514
+#endif
+
+/* Define this if you have a software controlled poweroff */
+#define HAVE_SW_POWEROFF
+
+/* Some Sansa E200s seem to be FAT16 formatted */
+#define HAVE_FAT16SUPPORT
+
+/* The number of bytes reserved for loadable codecs */
+#define CODEC_SIZE 0x80000
+
+/* The number of bytes reserved for loadable plugins */
+#define PLUGIN_BUFFER_SIZE 0x80000
+
+#define AB_REPEAT_ENABLE 1
+
+/* FM Tuner */
+#if 0 /* TODO: Rapsody models */
+#define CONFIG_TUNER LV24020LP
+#define HAVE_TUNER_PWR_CTRL
+#endif
+
+/* Define this for LCD backlight available */
+#define HAVE_BACKLIGHT
+#define HAVE_BACKLIGHT_BRIGHTNESS
+
+/* define this if the unit uses a scrollwheel for navigation */
+#define HAVE_SCROLLWHEEL
+/* define from which rotation speed [degree/sec] on the acceleration starts */
+#define WHEEL_ACCEL_START 540
+/* define type of acceleration (1 = ^2, 2 = ^3, 3 = ^4) */
+#define WHEEL_ACCELERATION 1
+
+/* define this if you have a flash memory storage */
+#define HAVE_FLASH_STORAGE
+
+#define BATTERY_CAPACITY_DEFAULT 750    /* default battery capacity */
+#define BATTERY_CAPACITY_MIN 750        /* min. capacity selectable */
+#define BATTERY_CAPACITY_MAX 750        /* max. capacity selectable */
+#define BATTERY_CAPACITY_INC 0          /* capacity increment */
+#define BATTERY_TYPES_COUNT  1          /* only one type */
+
+/* Hardware controlled charging? FIXME */
+#define CONFIG_CHARGING CHARGING_SIMPLE
+
+/* define this if the unit can be powered or charged via USB */
+#define HAVE_USB_POWER
+
+/** Non-simulator section **/
+#ifndef SIMULATOR
+
+/* Define this if you have a PortalPlayer PP5024 */
+#define CONFIG_CPU AS3525
+
+/* Define this if you want to use the AS352X i2c interface */
+#define CONFIG_I2C I2C_AS352X
+
+/* define this if the hardware can be powered off while charging */
+/* Sansa can't be powered off while charging */
+/* #define HAVE_POWEROFF_WHILE_CHARGING */
+
+/* The start address index for ROM builds */
+#define ROM_START 0x00000000
+
+/* Define this to the CPU frequency */
+#define CPU_FREQ         75000000 /* TODO: Check frequency from uboot src */
+
+/* Type of LCD TODO: hopefully the same as the x5 but check this*/
+#define CONFIG_LCD LCD_X5
+
+/* Offset ( in the firmware file's header ) to the file CRC and data. These are
+   only used when loading the old format rockbox.e200 file */
+#define FIRMWARE_OFFSET_FILE_CRC    0x0
+#define FIRMWARE_OFFSET_FILE_DATA   0x8
+
+#ifndef BOOTLOADER
+#define HAVE_MULTIVOLUME
+#define HAVE_HOTSWAP
+#endif
+
+/* #define USB_IPODSTYLE */
+
+/* USB On-the-go */
+#define CONFIG_USBOTG USBOTG_ARC
+
+/* enable these for the experimental usb stack */
+#define HAVE_USBSTACK
+#define USB_VENDOR_ID 0x0781
+#define USB_PRODUCT_ID 0x7421
+
+/* Virtual LED (icon) */
+#define CONFIG_LED LED_VIRTUAL
+
+/* Define this if you have adjustable CPU frequency */
+#define HAVE_ADJUSTABLE_CPU_FREQ
+
+#define MI4_FORMAT
+#define BOOTFILE_EXT    "bin"
+#define BOOTFILE        "rockbox." BOOTFILE_EXT
+#define OLD_BOOTFILE    "rockbox.e200v2"
+#define BOOTDIR "/.rockbox"
+
+#define ICODE_ATTR_TREMOR_NOT_MDCT
+
+#define INCLUDE_TIMEOUT_API
+
+#endif /* SIMULATOR */
+
+/** Port-specific settings **/
+
+/* Main LCD backlight brightness range and defaults */
+#define MIN_BRIGHTNESS_SETTING      1
+#define MAX_BRIGHTNESS_SETTING     12
+#define DEFAULT_BRIGHTNESS_SETTING  6
+
+/* Default recording levels */
+#define DEFAULT_REC_MIC_GAIN    23
+#define DEFAULT_REC_LEFT_GAIN   23
+#define DEFAULT_REC_RIGHT_GAIN  23
+
+#ifdef E200R_INSTALLER
+#define IRAMORIG 0x40004000
+#endif
+

Property changes on: firmware/export/config-e200v2.h
___________________________________________________________________
Name: svn:eol-style
 +native
Name: svn:keywords
 +Author Date Id Revision

=== firmware/export/powermgmt.h
==================================================================
--- firmware/export/powermgmt.h	(revision 16933)
+++ firmware/export/powermgmt.h	(patch as352x level 1)
@@ -116,7 +116,7 @@
 #if defined(HAVE_RECORDING)
 # define CURRENT_RECORD     35  /* FIXME: this needs adjusting */
 #endif
-#elif defined(SANSA_E200)    /* Sandisk E200v1  */
+#elif defined(SANSA_E200) || defined(SANSA_E200_V2)   /* Sandisk E200v1/v2  */
 # define CURRENT_NORMAL     45  /* Mike's measurements in Jan 2008  */
 # define CURRENT_BACKLIGHT  40  /* Screen is about 20, blue LEDs are another 20, so 40 if both */
 # define CURRENT_RECORD     40  /* flash player, so this is just unboosted current*/
=== firmware/export/as352x.h
==================================================================
--- firmware/export/as352x.h	(revision 16933)
+++ firmware/export/as352x.h	(patch as352x level 1)
@@ -0,0 +1,397 @@
+/*
+* (C) Copyright 2006
+* Copyright (C) 2006 Austriamicrosystems, by thomas.luo
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+#ifndef __AS352X_H__
+#define __AS352X_H__
+
+#define AS352X_UART_CHANNELS 1
+
+/* AS352X only supports 512 Byte HW ECC */
+#define AS352X_ECCSIZE 512
+#define AS352X_ECCBYTES 3
+
+
+/* AS352X device base addresses */
+
+
+/*
+------------------------------------------------------------------------
+*  AS352X Registers
+*
+------------------------------------------------------------------------
+*
+*/
+
+
+/* AHB */
+#define AS352X_USB_BASE            0xC6000000
+#define AS352X_VIC_BASE            0xC6010000
+#define AS352X_DMAC_BASE           0xC6020000
+#define AS352X_MPMC_BASE   0xC6030000
+#define AS352X_MEMSTICK_BASE       0xC6040000
+#define AS352X_CF_IDE_BASE         0xC6050000
+
+/* APB */
+#define AS352X_NAND_FLASH_BASE     0xC8000000
+#define AS352X_BIST_MANAGER_BASE   0xC8010000
+#define AS352X_SD_MCI_BASE         0xC8020000
+#define AS352X_TIMER_BASE          0xC8040000
+#define AS352X_WDT_BASE            0xC8050000
+#define AS352X_I2C_MS_BASE         0xC8060000
+#define AS352X_I2C_AUDIO_BASE      0xC8070000
+#define AS352X_SSP_BASE            0xC8080000
+#define AS352X_I2SIN_BASE          0xC8090000
+#define AS352X_I2SOUT_BASE         0xC80A0000
+#define AS352X_GPIO1_BASE          0xC80B0000
+#define AS352X_GPIO2_BASE          0xC80C0000
+#define AS352X_GPIO3_BASE          0xC80D0000
+#define AS352X_GPIO4_BASE          0xC80E0000
+#define AS352X_CGU_BASE            0xC80F0000
+#define AS352X_CCU_BASE            0xC8100000
+#define AS352X_UART0_BASE           0xC8110000
+#define AS352X_DBOP_BASE            0xC8120000
+
+
+
+
+
+
+
+
+/*
+------------------------------------------------------------------------
+*  AS352X control registers
+*
+------------------------------------------------------------------------
+*/
+
+#define CCU_SRC           ( (AS352X_CCU_BASE) + 0x00)
+#define CCU_SRL           ( (AS352X_CCU_BASE) + 0x04)
+#define CCU_MEMMAP        ( (AS352X_CCU_BASE) + 0x08)
+#define CCU_IO            ( (AS352X_CCU_BASE) + 0x0C)
+#define CCU_SCON          ( (AS352X_CCU_BASE) + 0x10)
+#define CCU_VERS          ( (AS352X_CCU_BASE) + 0x14)
+
+
+/**
+* Reset Control Lines in CCU_SRC register
+**/
+#define CCU_SRC_DBOP_EN        ( 1 << 24 )
+#define CCU_SRC_SPDIF_EN       ( 1 << 22 )
+#define CCU_SRC_TIMER_EN       ( 1 << 21 )
+#define CCU_SRC_SSP_EN         ( 1 << 20 )
+#define CCU_SRC_WDO_EN         ( 1 << 19 )
+#define CCU_SRC_IDE_EN         ( 1 << 18 )
+#define CCU_SRC_IDE_AHB_EN     ( 1 << 17 )
+#define CCU_SRC_UART0           ( 1 << 16 )
+#define CCU_SRC_NAF_EN         ( 1 << 15 )
+#define CCU_SRC_SDMCI_EN       ( 1 << 14 )
+#define CCU_SRC_GPIO_EN        ( 1 << 13 )
+#define CCU_SRC_I2C_AUDIO_EN   ( 1 << 12 )
+#define CCU_SRC_I2C_EN         ( 1 << 11 )
+#define CCU_SRC_MST_EN         ( 1 << 10 )
+#define CCU_SRC_I2SIN          ( 1 <<  9 )
+#define CCU_SRC_I2SOUT         ( 1 <<  8 )
+#define CCU_SRC_USB_AHB_EN     ( 1 <<  7 )
+#define CCU_SRC_USB_PHY_EN     ( 1 <<  6 )
+#define CCU_SRC_DMAC_EN        ( 1 <<  5 )
+#define CCU_SRC_VIC_EN         ( 1 <<  4 )
+
+/**
+* Magic number for CCU_SRL for reset.
+**/
+#define CCU_SRL_MAGIC_NUMBER      0x1A720212
+
+/**
+* Chip select lines for NAF. Use these constants to select/deselct the
+CE lines
+* for NAND flashes in Register CCU_IO.
+**/
+#define CCU_IO_NAF_CE_LINE_0      ( 0 << 7 )
+#define CCU_IO_NAF_CE_LINE_1      ( 1 << 7 )
+#define CCU_IO_NAF_CE_LINE_2      ( 2 << 7 )
+#define CCU_IO_NAF_CE_LINE_3      ( 3 << 7 )
+
+/* CCU IO Select/Deselect IDE */
+#define CCU_IO_IDE                ( 1 << 5 )
+
+/* CCU IO Select/desect I2C */
+#define CCU_IO_I2C_MASTER_SLAVE   ( 1 << 1 )
+
+/* CCU IO Select/desect UART */
+#define CCU_IO_UART0               ( 1 << 0 )
+
+
+#define CCU_RESET_ALL_BUT_MEMORY \
+ ( CCU_SRC_DBOP_EN        \
+ | CCU_SRC_SPDIF_EN       \
+ | CCU_SRC_TIMER_EN       \
+ | CCU_SRC_SSP_EN         \
+ | CCU_SRC_WDO_EN         \
+ | CCU_SRC_IDE_EN         \
+ | CCU_SRC_IDE_AHB_EN     \
+ | CCU_SRC_UART0           \
+ | CCU_SRC_NAF_EN         \
+ | CCU_SRC_SDMCI_EN       \
+ | CCU_SRC_GPIO_EN        \
+ | CCU_SRC_I2C_AUDIO_EN   \
+ | CCU_SRC_I2C_EN         \
+ | CCU_SRC_MST_EN         \
+ | CCU_SRC_I2SIN          \
+ | CCU_SRC_I2SOUT         \
+ | CCU_SRC_USB_AHB_EN     \
+ | CCU_SRC_USB_PHY_EN     \
+ | CCU_SRC_DMAC_EN        \
+ | CCU_SRC_VIC_EN         \
+ )
+
+/**
+* Magic number for CCU_SRL for reset.
+**/
+#define CCU_SRL_MAGIC_NUMBER      0x1A720212
+
+/**
+* Chip select lines for NAF. Use these constants to select/deselct the
+CE lines
+* for NAND flashes in Register CCU_IO.
+**/
+#define CCU_IO_NAF_CE_LINE_0      ( 0 << 7 )
+#define CCU_IO_NAF_CE_LINE_1      ( 1 << 7 )
+#define CCU_IO_NAF_CE_LINE_2      ( 2 << 7 )
+#define CCU_IO_NAF_CE_LINE_3      ( 3 << 7 )
+
+/* CCU IO Select/Deselect IDE */
+#define CCU_IO_IDE                ( 1 << 5 )
+
+/* CCU IO Select/desect I2C */
+#define CCU_IO_I2C_MASTER_SLAVE   ( 1 << 1 )
+
+/* CCU IO Select/desect UART */
+#define CCU_IO_UART               ( 1 << 0 )
+/*
+------------------------------------------------------------------------
+*  AS352X clock control registers
+*
+------------------------------------------------------------------------
+*/
+
+#define CGU_REG_PLLA         ( (AS352X_CGU_BASE) + 0x00 )
+#define CGU_REG_PLLB         ( (AS352X_CGU_BASE) + 0x04 )
+#define CGU_REG_PLLASUP      ( (AS352X_CGU_BASE) + 0x08 )
+#define CGU_REG_PLLBSUP      ( (AS352X_CGU_BASE) + 0x0C )
+#define CGU_REG_PROC         ( (AS352X_CGU_BASE) + 0x10 )
+#define CGU_REG_PERI         ( (AS352X_CGU_BASE) + 0x14 )
+#define CGU_REG_AUDIO        ( (AS352X_CGU_BASE) + 0x18 )
+#define CGU_REG_USB          ( (AS352X_CGU_BASE) + 0x1C )
+#define CGU_REG_INTCTRL      ( (AS352X_CGU_BASE) + 0x20 )
+#define CGU_REG_IRQ          ( (AS352X_CGU_BASE) + 0x24 )
+#define CGU_REG_COUNTA       ( (AS352X_CGU_BASE) + 0x28 )
+#define CGU_REG_COUNTB       ( (AS352X_CGU_BASE) + 0x2C )
+#define CGU_REG_IDE          ( (AS352X_CGU_BASE) + 0x30 )
+#define CGU_REG_MEMSTICK     ( (AS352X_CGU_BASE) + 0x34 )
+#define CGU_REG_DBOP         ( (AS352X_CGU_BASE) + 0x38 )
+
+
+/* --- are disabled after reset --- */
+#define CGU_DMA_CLOCK_ENABLE                 ( 1 << 22 ) /* dma */
+#define CGU_USB_CLOCK_ENABLE                 ( 1 << 21 ) /* usb */
+#define CGU_I2SOUT_APB_CLOCK_ENABLE          ( 1 << 20 ) /* i2sout */
+#define CGU_I2SIN_APB_CLOCK_ENABLE           ( 1 << 19 ) /* i2sin */
+#define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE    ( 1 << 18 ) /* i2c
+master/slave */
+#define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE    ( 1 << 17 ) /* i2c audio
+master */
+#define CGU_GPIO_CLOCK_ENABLE                ( 1 << 16 ) /* gpio */
+#define CGU_MCI_CLOCK_ENABLE                 ( 1 << 15 ) /* mmc + sd */
+#define CGU_NAF_CLOCK_ENABLE                 ( 1 << 14 ) /* naf */
+#define CGU_UART_APB_CLOCK_ENABLE            ( 1 << 13 ) /* uart */
+#define CGU_WDOCNT_CLOCK_ENABLE              ( 1 << 12 ) /* watchdog
+counter */
+#define CGU_WDOIF_CLOCK_ENABLE               ( 1 << 11 ) /* watchdog
+timer module */
+#define CGU_SSP_CLOCK_ENABLE                 ( 1 << 10 ) /* ssp */
+#define CGU_TIMER1_CLOCK_ENABLE              ( 1 <<  9 ) /* timer 1 */
+#define CGU_TIMER2_CLOCK_ENABLE              ( 1 <<  8 ) /* timer 2 */
+#define CGU_TIMERIF_CLOCK_ENABLE             ( 1 <<  7 ) /* timer
+interface */
+
+/**  ------------------------------------------------------------------
+* Number of cycles to wait before cgu is safely locked.
+**/
+#define CGU_LOCK_CNT 0xFF
+
+/* FIFO depth is 16 for tx and rx fifo */
+#define UART_FIFO_DEPTH           16
+
+/* ------------------- UART Line Control Register bit fields
+-------------------- */
+
+#define UART_LNCTL_DLSEN          (1 << 7) /* Device latch select bit
+*/
+
+
+/* --------------   UART Interrupt Control Register bit fields
+--------------- */
+
+#define UART_INTR_RXDRDY           0x1 /* Data ready interrupt
+*/
+#define UART_INTR_TXEMT            0x2 /* Transmit data empty interrupt
+*/
+#define UART_INTR_RXLINESTATUS     0x4 /* Receive line status interrupt
+*/
+
+/* ------------------- UART Line Status Register bit fields
+--------------------  */
+
+#define UART_ERRORBITS             0x1E
+#define UART_RX_DATA_READY        (1 << 0)
+#define UART_TX_HOLD_REG_EMPTY    (1 << 5)
+
+/* -------------------        FIFO CNTL Register contants
+-------------------*/
+
+#define UART_FIFO_EN              (1 << 0)  /* Enable the UART FIFO
+*/
+#define UART_TX_FIFO_RST          (1 << 1)  /* Enable the UART FIFO
+*/
+#define UART_RX_FIFO_RST          (1 << 2)
+#define UART_RXFIFO_TRIGLVL_1     (0 << 4) /* RX FIFO TRIGGER_LEVEL 1
+*/
+#define UART_RXFIFO_TRIGLVL_4      0x08    /* RX FIFO TRIGGER_LEVEL 4
+*/
+#define UART_RXFIFO_TRIGLVL_8      0x10    /* RX FIFO TRIGGER_LEVEL 8
+*/
+#define UART_RXFIFO_TRIGLVL_14     0x18    /* RX FIFO TRIGGER_LEVEL 14
+*/
+
+
+/* -------------------        FIFO status Register contants
+------------------*/
+#define UART_TX_FIFO_FULL         (1 << 0)
+#define UART_RX_FIFO_FULL         (1 << 1)
+#define UART_TX_FIFO_EMPTY        (1 << 2)
+#define UART_RX_FIFO_EMPTY        (1 << 3)
+
+
+/* ----------------------- defines
+---------------------------------------- */
+
+#define UART_DATA_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Data
+register */      
+#define UART_DLO_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Clock
+divider(lower byte) register */
+#define UART_DHI_REG ( (AS352X_UART0_BASE) + 0x04 ) /* Clock
+divider(higher byte) register */
+#define UART_INTEN_REG ( (AS352X_UART0_BASE) + 0x04 ) /*
+Interrupt enable register */
+#define UART_INTSTATUS_REG ( (AS352X_UART0_BASE) + 0x08 ) /*
+Interrupt status register */
+#define UART_FCTL_REG            ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo
+control  register */
+#define UART_FSTATUS_REG         ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo
+status register */
+#define UART_LNCTL_REG           ( (AS352X_UART0_BASE) + 0x10 ) /* Line
+control register */
+#define UART_LNSTATUS_REG        ( (AS352X_UART0_BASE) + 0x14 ) /* Line
+status register */
+
+
+#define TIMER_LOAD       ( (AS352X_TIMER_BASE) + 0x00 ) /* 32-bit width
+*/
+#define TIMER_VALUE      ( (AS352X_TIMER_BASE) + 0x04 ) /* 32 bit width
+*/
+#define TIMER_CONTROL    ( (AS352X_TIMER_BASE) + 0x08 ) /*  8 bit width
+*/
+#define TIMER_INTCLR     ( (AS352X_TIMER_BASE) + 0x0C ) /* clears ir by
+write access */
+#define TIMER_RIS        ( (AS352X_TIMER_BASE) + 0x10 ) /*  1 bit width
+*/
+#define TIMER_MIS        ( (AS352X_TIMER_BASE) + 0x14 ) /*  1 bit width
+*/
+
+/**
+* Counter/Timer control register bits
+**/
+#define TIMER_ENABLE       0x80
+#define TIMER_PERIODIC     0x40
+#define TIMER_INT_ENABLE   0x20
+#define TIMER_32_BIT   0x02
+#define TIMER_ONE_SHOT   0x01
+#define TIMER_PRESCALE_1   0x00
+#define TIMER_PRESCALE_16   0x04
+#define TIMER_PRESCALE_256 0x08
+
+
+
+#define NAF_CONFIG         ( (AS352X_NAND_FLASH_BASE) + 0x00 )
+#define NAF_CONTROL        ( (AS352X_NAND_FLASH_BASE) + 0x04 )
+#define NAF_ECC            ( (AS352X_NAND_FLASH_BASE) + 0x08 )
+#define NAF_DATA           ( (AS352X_NAND_FLASH_BASE) + 0x0C )
+#define NAF_MODE           ( (AS352X_NAND_FLASH_BASE) + 0x10 )
+#define NAF_STATUS         ( (AS352X_NAND_FLASH_BASE) + 0x14 )
+#define NAF_MASK           ( (AS352X_NAND_FLASH_BASE) + 0x18 )
+#define NAF_FIFODATA       ( (AS352X_NAND_FLASH_BASE) + 0x1C )
+#define NAF_WORDS          ( (AS352X_NAND_FLASH_BASE) + 0x20 )
+#define NAF_CLEAR          ( (AS352X_NAND_FLASH_BASE) + 0x24 )
+#define NAF_TEST           ( (AS352X_NAND_FLASH_BASE) + 0x28 )
+
+
+
+#define set_reg_bits32( registerAddress, value ) \
+ ( *( (volatile uint32_t *)(registerAddress) ) |= ( (uint32_t)(value) ) )
+
+
+#define clr_reg_bits32( registerAddress, value ) \
+ ( *( (volatile uint32_t *)(registerAddress) ) &= ( ~( (uint32_t)(value) ) ) )
+
+#define rreg32( registerAddress ) \
+ ( *( ( const volatile uint32_t * )( registerAddress ) ) )
+
+#define wreg32( registerAddress, value ) \
+ ( *( (volatile uint32_t *)(registerAddress) ) = ( (uint32_t)(value) ) )
+
+
+
+#define rreg16( registerAddress ) \
+ ( *( ( const volatile uint16_t * )( registerAddress ) ) )
+
+#define wreg16( registerAddress, value ) \
+ ( *( (volatile uint16_t *)(registerAddress) ) = ( (uint16_t)(value) ) )
+
+#define set_reg_bits16( registerAddress, value ) \
+ ( *( (volatile uint16_t *)(registerAddress) ) |= ( (uint16_t)(value) ) )
+
+#define clr_reg_bits16( registerAddress, value ) \
+ ( *( (volatile uint16_t *)(registerAddress) ) &= ( ~( (uint16_t)(value) ) ) )
+
+
+#define rreg8( registerAddress ) \
+ ( *( ( const volatile uint8_t * )( registerAddress ) ) )
+
+#define wreg8( registerAddress, value ) \
+ ( *( (volatile uint8_t *)(registerAddress) ) = ( (uint8_t)(value) ) )
+
+#define set_reg_bits8( registerAddress, value ) \
+ ( *( (volatile uint8_t *)(registerAddress) ) |= ( (uint8_t)(value) ) )
+
+#define clr_reg_bits8( registerAddress, value ) \
+ ( *( (volatile uint8_t *)(registerAddress) ) &= ( ~( (uint8_t)(value) ) ) )
+/* Wait until rINTPND is changed for the case that the ISR is very
+short. */
+#endif /*__AS352X_H__*/

Property changes on: firmware/export/as352x.h
___________________________________________________________________
Name: svn:eol-style
 +native
Name: svn:keywords
 +"HeadURL Id LastChangedBy LastChangedDate LastChangedRevision"
Name: svn:mime-type
 +text/x-c++hdr

=== firmware/export/config.h
==================================================================
--- firmware/export/config.h	(revision 16933)
+++ firmware/export/config.h	(patch as352x level 1)
@@ -40,6 +40,7 @@
 
 /* CONFIG_CPU */
 #define SH7034       7034
+#define AS3525       3525
 #define MCF5249      5249
 #define MCF5250      5250
 #define PP5002       5002
@@ -143,6 +144,7 @@
 #define I2C_IMX31L   9
 #define I2C_TCC77X  10
 #define I2C_TCC780X 11
+#define I2C_AS352X  12 /* AS352X style */
 
 /* CONFIG_LED */
 #define LED_REAL     1 /* SW controlled LED (Archos recorders, player) */
@@ -230,6 +232,8 @@
 #include "config-h10_5gb.h"
 #elif defined(SANSA_E200)
 #include "config-e200.h"
+#elif defined(SANSA_E200_V2)
+#include "config-e200v2.h"
 #elif defined(SANSA_C200)
 #include "config-c200.h"
 #elif defined(ELIO_TPJ1022)
@@ -346,6 +350,12 @@
 #define CPU_SH
 #endif
 
+/* define for all cpus from AS352x family
+ */
+#if (CONFIG_CPU == AS3525)
+#define CPU_AS352X
+#endif
+
 /* define for all cpus from coldfire family */
 #if (CONFIG_CPU == MCF5249) || (CONFIG_CPU == MCF5250)
 #define CPU_COLDFIRE
@@ -374,6 +384,11 @@
 #define CPU_ARM7TDMI
 #endif
 
+/* define for all cpus from ARM9TDMI family (for specific optimisations) */
+#if defined(CPU_AS352X)
+#define CPU_ARM9TDMI
+#endif
+
 /* define for all cpus from ARM family */
 #if (CONFIG_CPU == IMX31L)
 #define CPU_ARM
@@ -386,7 +401,7 @@
 #endif
 
 #if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \
-  || (CONFIG_CPU == DSC25) || (CONFIG_CPU == DM320)
+  || (CONFIG_CPU == DSC25) || (CONFIG_CPU == DM320) || defined(CPU_AS352X)
 #define CPU_ARM
 #define ARM_ARCH 4 /* ARMv4 */
 #endif
@@ -411,6 +426,7 @@
 /* IRAM usage */
 #if !defined(SIMULATOR) &&   /* Not for simulators */ \
     (((CONFIG_CPU == SH7034) && !defined(PLUGIN)) || /* SH1 archos: core only */ \
+    defined(CPU_AS352X) || /* TODO: Check this: AS352X: core, plugins, codecs */ \
     defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \
     defined(CPU_PP) ||  /* PortalPlayer: core, plugins, codecs */ \
     defined(CPU_TCC77X) ||  /* Telechips: core, plugins, codecs */ \
=== firmware/export/as3514.h
==================================================================
--- firmware/export/as3514.h	(revision 16933)
+++ firmware/export/as3514.h	(patch as352x level 1)
@@ -72,7 +72,10 @@
 #define VOLUME_MIN -735
 #define VOLUME_MAX   60
 
-#if defined(SANSA_E200) || defined(SANSA_C200)
+/* TODO: Check wether e200v2 has an AS3514 on SoC
+ *       and wether i2c addr is correct for e200v2
+ */
+#if defined(SANSA_E200) || defined(SANSA_E200_V2) || defined(SANSA_C200)
 #define AS3514_I2C_ADDR 0x46
 #endif
 
=== firmware/SOURCES
==================================================================
--- firmware/SOURCES	(revision 16933)
+++ firmware/SOURCES	(patch as352x level 1)
@@ -311,6 +311,10 @@
 #elif CONFIG_I2C == I2C_S3C2440
 /* no i2c driver yet */
 #endif
+#if defined(CPU_AS352X)
+target/arm/as352x/nand-as352x.c
+target/arm/as352x/system-as352x.c
+#endif
 #if CONFIG_CPU == PNX0101
 target/arm/pnx0101/system-pnx0101.c
 #endif
@@ -329,6 +333,8 @@
 #endif /* SANSA_E200 */
 target/arm/crt0-pp.S
 #endif
+#elif defined(CPU_AS352X)
+target/arm/as352x/crt0.S
 #elif CONFIG_CPU == PNX0101
 target/arm/pnx0101/crt0-pnx0101.S
 #elif CONFIG_CPU==DM320
@@ -417,18 +423,24 @@
 #endif /* SIMULATOR */
 #endif /* ARCHOS_ONDIOFM || ARCHOS_ONDIOFM */
 
-#ifdef SANSA_E200
+#if defined(SANSA_E200) || defined(SANSA_E200_V2)
 #ifndef SIMULATOR
 target/arm/lcd-as-memframe.S
+#ifdef SANSA_E200
 target/arm/sandisk/ata-c200_e200.c
+#endif
 target/arm/sandisk/sansa-e200/lcd-e200.c
 target/arm/sandisk/adc-c200_e200.c
 target/arm/sandisk/backlight-c200_e200.c
+#ifdef CPU_PP
 target/arm/usb-fw-pp502x.c
+#endif
 target/arm/sandisk/sansa-e200/button-e200.c
 target/arm/sandisk/power-c200_e200.c
 target/arm/sandisk/sansa-e200/powermgmt-e200.c
+#ifdef CPU_PP
 target/arm/i2s-pp.c
+#endif
 #ifndef BOOTLOADER
 target/arm/sandisk/audio-c200_e200.c
 #endif /* BOOTLOADER */
=== firmware/target/arm/system-target.h
==================================================================
--- firmware/target/arm/system-target.h	(revision 16933)
+++ firmware/target/arm/system-target.h	(patch as352x level 1)
@@ -22,6 +22,14 @@
 
 #include "system-arm.h"
 
+#ifdef CPU_AS352X
+
+#define CPUFREQ_SLEEP       32768
+#define CPUFREQ_DEFAULT  24000000
+#define CPUFREQ_NORMAL   24000000
+#define CPUFREQ_MAX     192000000
+
+#endif
 #ifdef CPU_PP
 /* TODO: This header is actually portalplayer specific, and should be
  * moved into an appropriate subdir (or even split in 2). */
=== firmware/target/arm/cpu-arm922t.c
==================================================================
--- firmware/target/arm/cpu-arm922t.c	(revision 16933)
+++ firmware/target/arm/cpu-arm922t.c	(patch as352x level 1)
@@ -0,0 +1,193 @@
+/*
+* (C) Copyright 2002
+* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+* Marius Groeger <mgroeger@...>
+*
+* (C) Copyright 2002
+* Gary Jennejohn, DENX Software Engineering, <gj@...>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+/*
+* CPU specific code
+*/
+
+#include <common.h>
+#include <command.h>
+#include <arm922t.h>
+
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long
+read_p15_c1 (void)
+{
+    unsigned long value;
+
+    __asm__
+        __volatile__ ("mrc p15, 0, %0, c1, c0, 0   @ read control reg\n":"=r"
+                      (value)::"memory");
+
+#ifdef MMU_DEBUG
+    printf ("p15/c1 is = %08lx\n", value);
+#endif
+    return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void
+write_p15_c1 (unsigned long value)
+{
+#ifdef MMU_DEBUG
+    printf ("write %08lx to p15/c1\n", value);
+#endif
+    __asm__
+        __volatile__ ("mcr p15, 0, %0, c1, c0, 0   @ write it back\n"::"r"
+                      (value):"memory");
+
+    read_p15_c1 ();
+}
+
+static void
+cp_delay (void)
+{
+    volatile int i;
+
+    /* copro seems to need some delay between reading and writing */
+    for (i = 0; i < 100; i++);
+}
+
+/* See also ARM920T    Technical reference Manual */
+#define C1_MMU (1<<0)           /* mmu off/on */
+#define C1_ALIGN (1<<1)         /* alignment faults off/on */
+#define C1_DC (1<<2)            /* dcache off/on */
+
+#define C1_BIG_ENDIAN (1<<7)    /* big endian off/on */
+#define C1_SYS_PROT (1<<8)      /* system protection */
+#define C1_ROM_PROT (1<<9)      /* ROM protection */
+#define C1_IC (1<<12)           /* icache off/on */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors:
+                                   low/high addresses */
+
+
+int
+cpu_init (void)
+{
+    /*
+     * setup up stacks if necessary
+     */
+#ifdef CONFIG_USE_IRQ
+    IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+    FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+    return 0;
+}
+
+int
+cleanup_before_linux (void)
+{
+    /*
+     * this function is called just before we call linux
+     * it prepares the processor for linux
+     *
+     * we turn off caches etc ...
+     */
+
+    unsigned long i;
+
+    disable_interrupts ();
+
+    /* turn off I/D-cache */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    i &= ~(C1_DC | C1_IC);
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+    /* flush I/D-cache */
+    i = 0;
+    asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+
+    return (0);
+}
+
+int
+do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+    disable_interrupts ();
+    reset_cpu (0);
+     /*NOTREACHED*/ return (0);
+}
+
+void
+icache_enable (void)
+{
+    ulong reg;
+
+    reg = read_p15_c1 ();       /* get control reg. */
+    cp_delay ();
+    write_p15_c1 (reg | C1_IC);
+}
+
+void
+icache_disable (void)
+{
+    ulong reg;
+
+    reg = read_p15_c1 ();
+    cp_delay ();
+    write_p15_c1 (reg & ~C1_IC);
+}
+
+int
+icache_status (void)
+{
+    return (read_p15_c1 () & C1_IC) != 0;
+}
+
+#ifdef USE_922T_MMU
+/* It makes no sense to use the dcache if the MMU is not enabled */
+void
+dcache_enable (void)
+{
+    ulong reg;
+
+    reg = read_p15_c1 ();
+    cp_delay ();
+    write_p15_c1 (reg | C1_DC);
+}
+
+void
+dcache_disable (void)
+{
+    ulong reg;
+
+    reg = read_p15_c1 ();
+    cp_delay ();
+    reg &= ~C1_DC;
+    write_p15_c1 (reg);
+}
+
+int
+dcache_status (void)
+{
+    return (read_p15_c1 () & C1_DC) != 0;
+}
+#endif

Property changes on: firmware/target/arm/cpu-arm922t.c
___________________________________________________________________
Name: svn:eol-style
 +native
Name: svn:keywords
 +"HeadURL Id LastChangedBy LastChangedDate LastChangedRevision"
Name: svn:mime-type
 +text/x-csrc

=== firmware/target/arm/as352x/serial-as352x.c
==================================================================
--- firmware/target/arm/as352x/serial-as352x.c	(revision 16933)
+++ firmware/target/arm/as352x/serial-as352x.c	(patch as352x level 1)
@@ -0,0 +1,157 @@
+/*
+* Copyright (C) 2006 Austriamicrosystems Corporation
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include "config.h"
+#include <common.h>
+#if defined(CONFIG_AS352X)
+#include "as352x.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+* Initialise the serial port with the given baudrate. The settings
+* are always 8 data bits, no parity, 1 stop bit, no start bits.
+*/
+void
+serial_setbrg (void)
+{
+    uint8_t controlData;
+    set_reg_bits32 (CCU_IO, CCU_IO_UART);
+
+    /* reset the uart
+     */
+    set_reg_bits32 (CCU_SRC, CCU_SRC_UART0);
+    wreg32 (CCU_SRL, CCU_SRL_MAGIC_NUMBER);
+    clr_reg_bits32 (CCU_SRC, CCU_SRC_UART0);
+    wreg32 (CCU_SRL, 0x0);
+    wreg32 (UART_FCTL_REG, 0);
+    wreg32 (UART_INTEN_REG, 0);
+    controlData = 3;
+    wreg32 (UART_LNCTL_REG, controlData | UART_LNCTL_DLSEN);
+    wreg32 (UART_DLO_REG, 0x68);
+    wreg32 (UART_DHI_REG, 0x0);
+    wreg32 (UART_LNCTL_REG, controlData & (~UART_LNCTL_DLSEN));
+
+}
+
+int
+serial_init (void)
+{
+    int i;
+    serial_setbrg ();
+    for (i = 0; i < 100; i++);
+    return (0);
+}
+
+/*
+* Read a single byte from the serial port. Returns 1 on success, 0
+* otherwise. When the function is succesfull, the character read is
+* written into its argument c.
+*/
+int
+serial_getc (void)
+{
+    uint8_t c;
+
+    while (!(rreg32 (UART_LNSTATUS_REG) & UART_RX_DATA_READY));
+    c = rreg32 (UART_DATA_REG);
+    return c & 0xff;
+}
+
+#ifdef CONFIG_HWFLOW
+static int hwflow = 0;          /* turned off by default */
+int
+hwflow_onoff (int on)
+{
+    switch (on)
+      {
+      case 0:
+      default:
+          break;                /* return current */
+      case 1:
+          hwflow = 0;           /* turn on */
+          break;
+      case -1:
+          hwflow = 0;           /* turn off */
+          break;
+      }
+    return hwflow;
+}
+#endif
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int be_quiet = 0;
+void
+disable_putc (void)
+{
+    be_quiet = 1;
+}
+
+void
+enable_putc (void)
+{
+    be_quiet = 0;
+}
+#endif
+
+
+/*
+* Output a single byte to the serial port.
+*/
+void
+serial_putc (const char c)
+{
+#ifdef CONFIG_MODEM_SUPPORT
+    if (be_quiet)
+        return;
+#endif
+
+    /* wait for room in the tx FIFO */
+    while (!(rreg32 (UART_LNSTATUS_REG) & UART_TX_HOLD_REG_EMPTY));
+    wreg32 (UART_DATA_REG, c);
+
+
+
+    /* If \n, also do \r */
+    if (c == '\n')
+        serial_putc ('\r');
+}
+
+/*
+* Test whether a character is in the RX buffer
+*/
+int
+serial_tstc (void)
+{
+    return (rreg32 (UART_LNSTATUS_REG) & UART_RX_DATA_READY);
+}
+
+void
+serial_puts (const char *s)
+{
+    while (*s)
+      {
+          serial_putc (*s++);
+      }
+}
+
+#endif /* defined(CONFIG_AS352X) */

Property changes on: firmware/target/arm/as352x/serial-as352x.c
___________________________________________________________________
Name: svn:eol-style
 +native
Name: svn:keywords
 +"HeadURL Id LastChangedBy LastChangedDate LastChangedRevision"
Name: svn:mime-type
 +text/x-csrc

=== firmware/target/arm/as352x/nand-as352x.c
==================================================================
--- firmware/target/arm/as352x/nand-as352x.c	(revision 16933)
+++ firmware/target/arm/as352x/nand-as352x.c	(patch as352x level 1)
@@ -0,0 +1,430 @@
+/*
+ * Copyright (C) 2006 Austriamicrosystems Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "config.h"
+
+#if 0 && defined(HAVE_FLASH_STORAGE)
+
+#include "inttypes.h"
+#include "as352x.h"
+#include "nand.h"
+
+/*
+ * hardware specific access to control-lines
+ */
+
+#define NAF_X8_X16_CODE 0x03 /* only for big block nand */
+
+/**
+ * Power bit in NAF mode register.
+ **/
+#define NAF_POWER_ON  0x0C
+#define NAF_POWER_OFF 0x00
+
+/**
+ * NAF Config register bits.
+ **/
+#define NAF_X16            0x00000001
+#define NAF_FIFO_ENABLE    0x00000004
+#define NAF_DMA_ON         0x00000008
+
+#define NAF_READ_STROBE_H  0x00000020    /* read  strobe high is 4 PLCK
+cycles */
+#define NAF_READ_STROBE_L  0x00000400    /* read  strobe low  is 5 PLCK
+cycles */
+#define NAF_WRITE_STROBE_H 0x00003000    /* write strobe high is 4 PCLK
+cycles */
+#define NAF_WRITE_STROBE_L 0x00040000    /* write strobe high is 4 PCLK
+cycles */
+
+#define NAF_STROBE_CONFIG \
+        ( NAF_READ_STROBE_H | NAF_READ_STROBE_L | NAF_WRITE_STROBE_H | \
+          NAF_WRITE_STROBE_L )
+
+
+/**
+ * NAF modi
+ **/
+#define NAF_MODE_CLE 1<<0
+#define NAF_MODE_ALE 1<<1
+#define NAF_MODE_NCE 1<<4
+#define NAF_MODE_WP 1<<7
+
+#define NAF_MODE_DATA_READ_NO_ECC         0x14
+#define NAF_MODE_DATA_WRITE_ECC_RESET     0xF4
+#define NAF_MODE_DATA_WRITE_NO_ECC        0x94
+/*
+ * chip R/B detection
+ */
+static int as352x_read_status;
+
+static int as352x_nand_ready(void)
+{
+ return ( ( rreg16( NAF_STATUS ) & 0x0080 ) == 0x0080 );
+
+}
+static int as352x_nand_strobe(void)
+{
+ return ( ( rreg16( NAF_STATUS ) & 0x0100 ) == 0x0100 );
+}
+static int as352x_fifo_isfull(void)
+{
+ return ( ( rreg16( NAF_STATUS ) & 0x01000 ) );
+}
+
+static int as352x_fifo_isempty(void)
+{
+ return ( ( rreg16( NAF_STATUS ) & 0x0200 ) );
+}
+/**
+ * nand_read_byte - [DEFAULT] read one byte from the chip
+ * @mtd: MTD device structure
+ *
+ * Default read function for 8bit buswith
+ */
+static uint8_t as352x_nand_read_byte(void)
+{
+ uint8_t data;
+
+ wreg8 ( NAF_CONTROL, 0x1 ); /* generate read strobe */
+ while (!as352x_nand_strobe());
+ data = rreg16( NAF_DATA );
+ if (as352x_read_status)
+     data |= 0x80;
+ return data;
+}
+
+/**
+ * nand_write_byte - [DEFAULT] write one byte to the chip
+ * @mtd: MTD device structure
+ * @byte: pointer to data byte to write
+ *
+ * Default write function for 8it buswith
+ */
+static void as352x_nand_write_byte(uint8_t byte)
+{
+
+ wreg16( NAF_DATA, byte );
+ while (!as352x_nand_strobe());
+}
+
+void as352x_nand_wait_fifo_empty(void)
+{
+   while ( ( rreg16( NAF_STATUS ) & 0x0004 ) != 0x0004 ) ; /* wait for
+got empty and ready */
+}
+
+/**
+ * nand_write_buf - [DEFAULT] write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ *
+ * Default write function for 8bit buswith
+ */
+static void as352x_nand_write_buf(const uint8_t *buf, int len)
+{
+ int i;
+ uint32_t *p =(uint32_t *)buf;
+ /* struct nand_chip *this = mtd->priv;
+  * unused, incomplete
+  */
+ len /=4;
+ wreg8( NAF_CLEAR, 0x7f );  
+ wreg32( NAF_WORDS, len );  
+ for (i=0; i<len; i++)
+ {
+ while (as352x_fifo_isfull());
+ wreg32( NAF_FIFODATA, p[i] );
+ }
+ as352x_nand_wait_fifo_empty();
+}
+
+/**
+ * nand_read_buf - [DEFAULT] read chip data into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ *
+ * Default read function for 8bit buswith
+ */
+static void as352x_nand_read_buf(uint8_t *buf, int len)
+{
+ int i;
+ /*  struct nand_chip *this = mtd->priv;
+  * unused, incomplete
+  */
+ uint32_t *p =(uint32_t *)buf;
+ len /=4;
+ wreg8( NAF_CLEAR, 0x7f );  
+ wreg32( NAF_WORDS, len );
+ for (i=0; i<len; i++)
+ {
+ while (as352x_fifo_isempty());
+ p[i] = rreg32( NAF_FIFODATA );
+ }
+ as352x_nand_wait_fifo_empty( );
+}
+/**
+ * nand_verify_buf - [DEFAULT] Verify chip data against buffer
+ * @mtd: MTD device structure
+ * @buf: buffer containing the data to compare
+ * @len: number of bytes to compare
+ *
+ * Default verify function for 8bit buswith
+ */
+static int nand_verify_buf(const uint8_t *buf, int len)
+{
+ int i;
+
+ /* struct nand_chip *this = mtd->priv;
+  * unused, incomplete
+  */
+
+ for (i=0; i<len; i++)
+  if (buf[i] != as352x_nand_read_byte())
+   return -14; /*EFAULT; - Bad address */
+
+ return 0;
+}
+
+static void as352x_nand_hwcontrol(int cmd)
+{
+ /* struct nand_chip *this = mtd->priv;
+  * ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+  * unused, incomplete
+  */
+ switch (cmd)
+ {
+ case NAND_CTL_SETCLE:
+ {
+ set_reg_bits16 ( NAF_MODE, NAF_MODE_CLE
+);
+ }
+ break;
+ case NAND_CTL_CLRCLE:
+ clr_reg_bits16( NAF_MODE, NAF_MODE_CLE
+);
+ break;
+ case NAND_CTL_SETALE:
+ {
+ set_reg_bits16 ( NAF_MODE, NAF_MODE_ALE
+);
+
+ }
+ break;
+ case NAND_CTL_CLRALE:
+ clr_reg_bits16( NAF_MODE, NAF_MODE_ALE
+);
+ break;
+ case NAND_CTL_SETNCE:
+  set_reg_bits16 ( NAF_MODE, NAF_MODE_NCE );
+ break;
+ case NAND_CTL_CLRNCE:
+ clr_reg_bits16( NAF_MODE, NAF_MODE_NCE );
+ break;
+ case NAND_CTL_SETWP:
+ set_reg_bits16 ( NAF_MODE, NAF_MODE_WP );
+ break;
+ case NAND_CTL_CLRWP:
+ clr_reg_bits16( NAF_MODE, NAF_MODE_WP );
+ break;
+
+ }
+}
+/**
+ * nand_command_lp - [DEFAULT] Send command to NAND large page device
+ * @mtd: MTD device structure
+ * @command: the command to be sent
+ * @column: the column address for this command, -1 if none
+ * @page_addr: the page address for this command, -1 if none
+ *
+ * Send command to NAND device. This is the version for the new large
+page devices
+ * We dont have the seperate regions as we have in the small page
+devices.
+ * We must emulate NAND_CMD_READOOB to keep the code compatible.
+ *
+ */
+
+static void as352x_nand_command_lp (struct mtd_info *mtd, unsigned
+command, int column, int page_addr)
+{
+ register struct nand_chip *this = mtd->priv;
+
+ /* Emulate NAND_CMD_READOOB */
+ if (command == NAND_CMD_READOOB) {
+ column += mtd->oobblock;
+ command = NAND_CMD_READ0;
+ }
+
+ as352x_read_status =0;
+ switch (command)
+ {
+ case NAND_CMD_SEQIN:
+ case NAND_CMD_ERASE1:
+ case NAND_CMD_ERASE2:
+ {
+  wreg8( NAF_MASK,  0xFF );
+    wreg8( NAF_CLEAR, 0x7f );
+   }
+   case NAND_CMD_CACHEDPROG:
+ case NAND_CMD_PAGEPROG:
+ {
+ this->hwcontrol(mtd, NAND_CTL_SETWP);
+ }
+ break;
+ case NAND_CMD_READ0:
+  wreg8( NAF_MASK,  0xFF );
+    wreg8( NAF_CLEAR, 0x7f );
+    wreg8( NAF_MODE,NAF_MODE_DATA_READ_NO_ECC);
+ default:
+ this->hwcontrol(mtd, NAND_CTL_CLRWP);
+ }
+ /* Begin command latch cycle */
+ this->hwcontrol(mtd, NAND_CTL_SETCLE);
+ /* Write out the command to the device. */
+ this->write_byte(mtd, command);
+ /* End command latch cycle */
+ this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+
+ if (column != -1 || page_addr != -1) {
+ this->hwcontrol(mtd, NAND_CTL_SETALE);
+
+ /* Serially input address */
+ if (column != -1) {
+ /* Adjust columns for 16 bit buswidth */
+ if (this->options & NAND_BUSWIDTH_16)
+ column >>= 1;
+ this->write_byte(mtd, column & 0xff);
+ this->write_byte(mtd, column >> 8);
+ }
+ if (page_addr != -1) {
+ this->write_byte(mtd, (unsigned char) (page_addr
+& 0xff));
+ this->write_byte(mtd, (unsigned char)
+((page_addr >> 8) & 0xff));
+ /* One more address cycle for devices > 128MiB
+*/
+ if (this->chipsize > (128 << 20))
+ this->write_byte(mtd, (unsigned char)
+((page_addr >> 16) & 0xff));
+ }
+ /* Latch in address */
+ this->hwcontrol(mtd, NAND_CTL_CLRALE);
+ }
+
+ /*
+ * program and erase have their own busy handlers
+ * status and sequential in needs no delay
+ */
+ switch (command) {
+ case NAND_CMD_SEQIN:
+ {
+ wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_ECC_RESET );  
+ break;
+ }
+ case NAND_CMD_ERASE1:
+ case NAND_CMD_ERASE2:
+ break;
+ case NAND_CMD_STATUS:
+ as352x_read_status =1;
+ break;
+ case NAND_CMD_CACHEDPROG:
+
+ case NAND_CMD_PAGEPROG:
+ wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_NO_ECC );
+ break;
+
+
+ case NAND_CMD_RESET:
+ if (this->dev_ready)
+ break;
+ udelay(this->chip_delay);
+ this->hwcontrol(mtd, NAND_CTL_SETCLE);
+ this->write_byte(mtd, NAND_CMD_STATUS);
+ this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+ while ( !(this->read_byte(mtd) & 0x40));
+ return;
+
+ case NAND_CMD_READ0:
+ /* Begin command latch cycle */
+ this->hwcontrol(mtd, NAND_CTL_SETCLE);
+ /* Write out the start read command */
+ this->write_byte(mtd, NAND_CMD_READSTART);
+ /* End command latch cycle */
+ this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+ /* Fall through into ready check */
+
+ /* This applies to read commands */
+ default:
+ /*
+ * If we don't have access to the busy pin, we apply the
+given
+ * command delay
+ */
+ if (!this->dev_ready) {
+ udelay (this->chip_delay);
+ return;
+ }
+ }
+
+ /* Apply this short delay always to ensure that we do wait tWB
+in
+ * any case on any machine. */
+ ndelay (1000);
+ /* wait until command is processed */
+ while (!this->dev_ready(mtd));
+}
+
+
+void board_nand_init(struct nand_chip *nand)
+{
+ // clear all NAF chip select bits
+   clr_reg_bits32( CCU_IO , ( CCU_IO_NAF_CE_LINE_0 | CCU_IO_NAF_CE_LINE_1
+                            | CCU_IO_NAF_CE_LINE_2 | CCU_IO_NAF_CE_LINE_3
+                            ) );
+   set_reg_bits32( CCU_IO , CCU_IO_NAF_CE_LINE_0 );
+
+   /* configure NAF */
+   wreg8( NAF_MODE,  NAF_POWER_ON );   /* turn power on */
+   wreg8( NAF_MASK,  0xFF );
+   wreg8( NAF_CLEAR, 0x7f );  /* clear any pending error indication */
+
+   /* configure fifo on but dma still off */
+   wreg32( NAF_CONFIG, NAF_FIFO_ENABLE | NAF_STROBE_CONFIG );
+
+    /* 2. change into read mode */
+ wreg8 ( NAF_MODE, NAF_MODE_DATA_READ_NO_ECC );
+
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->hwcontrol = as352x_nand_hwcontrol;
+ nand->dev_ready = as352x_nand_ready;
+ nand->chip_delay = 18;
+ nand->read_byte = as352x_nand_read_byte;
+ nand->write_byte = as352x_nand_write_byte;
+ nand->read_buf = as352x_nand_read_buf;
+ nand->write_buf = as352x_nand_write_buf;
+ nand->cmdfunc = as352x_nand_command_lp;
+}
+#endif

Property changes on: firmware/target/arm/as352x/nand-as352x.c
___________________________________________________________________
Name: svn:eol-style
 +native
Name: svn:keywords
 +"HeadURL Id LastChangedBy LastChangedDate LastChangedRevision"
Name: svn:mime-type
 +text/x-csrc

=== firmware/target/arm/as352x/nand.h
==================================================================
--- firmware/target/arm/as352x/nand.h	(revision 16933)
+++ firmware/target/arm/as352x/nand.h	(patch as352x level 1)
@@ -0,0 +1,300 @@
+/*
+ *  linux/include/linux/mtd/nand.h
+ *
+ *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
+ *		       Steven J. Hill <sjhill@realitydiluted.com>
+ *		       Thomas Gleixner <tglx@linutronix.de>
+ *
+ * $Id$
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Info:
+ *   Contains standard defines and IDs for NAND flash devices
+ *
+ *  Changelog:
+ *   01-31-2000 DMW	Created
+ *   09-18-2000 SJH	Moved structure out of the Disk-On-Chip drivers
+ *			so it can be used by other NAND flash device
+ *			drivers. I also changed the copyright since none
+ *			of the original contents of this file are specific
+ *			to DoC devices. David can whack me with a baseball
+ *			bat later if I did something naughty.
+ *   10-11-2000 SJH	Added private NAND flash structure for driver
+ *   10-24-2000 SJH	Added prototype for 'nand_scan' function
+ *   10-29-2001 TG	changed nand_chip structure to support
+ *			hardwarespecific function for accessing control lines
+ *   02-21-2002 TG	added support for different read/write adress and
+ *			ready/busy line access function
+ *   02-26-2002 TG	added chip_delay to nand_chip structure to optimize
+ *			command delay times for different chips
+ *   04-28-2002 TG	OOB config defines moved from nand.c to avoid duplicate
+ *			defines in jffs2/wbuf.c
+ *   08-07-2002 TG	forced bad block location to byte 5 of OOB, even if
+ *			CONFIG_MTD_NAND_ECC_JFFS2 is not set
+ *   08-10-2002 TG	extensions to nand_chip structure to support HW-ECC
+ *
+ *   08-29-2002 tglx	nand_chip structure: data_poi for selecting
+ *			internal / fs-driver buffer
+ *			support for 6byte/512byte hardware ECC
+ *			read_ecc, write_ecc extended for different oob-layout
+ *			oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
+ *			NAND_YAFFS_OOB
+ *  11-25-2002 tglx	Added Manufacturer code FUJITSU, NATIONAL
+ *			Split manufacturer and device ID structures
+ *
+ *  02-08-2004 tglx	added option field to nand structure for chip anomalities
+ *  05-25-2004 tglx	added bad block table support, ST-MICRO manufacturer id
+ *			update of nand_chip structure description
+ */
+#ifndef __LINUX_MTD_NAND_H
+#define __LINUX_MTD_NAND_H
+
+/* This constant declares the max. oobsize / page, which
+ * is supported now. If you add a chip with bigger oobsize/page
+ * adjust this accordingly.
+ */
+#define NAND_MAX_OOBSIZE	64
+
+/*
+ * Constants for hardware specific CLE/ALE/NCE function
+*/
+/* Select the chip by setting nCE to low */
+#define NAND_CTL_SETNCE		1
+/* Deselect the chip by setting nCE to high */
+#define NAND_CTL_CLRNCE		2
+/* Select the command latch by setting CLE to high */
+#define NAND_CTL_SETCLE		3
+/* Deselect the command latch by setting CLE to low */
+#define NAND_CTL_CLRCLE		4
+/* Select the address latch by setting ALE to high */
+#define NAND_CTL_SETALE		5
+/* Deselect the address latch by setting ALE to low */
+#define NAND_CTL_CLRALE		6
+/* Set write protection by setting WP to high. Not used! */
+#define NAND_CTL_SETWP		7
+/* Clear write protection by setting WP to low. Not used! */
+#define NAND_CTL_CLRWP		8
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0		0
+#define NAND_CMD_READ1		1
+#define NAND_CMD_PAGEPROG	0x10
+#define NAND_CMD_READOOB	0x50
+#define NAND_CMD_ERASE1		0x60
+#define NAND_CMD_STATUS		0x70
+#define NAND_CMD_STATUS_MULTI	0x71
+#define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_READID		0x90
+#define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_RESET		0xff
+
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART	0x30
+#define NAND_CMD_CACHEDPROG	0x15
+
+/* Status bits */
+#define NAND_STATUS_FAIL	0x01
+#define NAND_STATUS_FAIL_N1	0x02
+#define NAND_STATUS_TRUE_READY	0x20
+#define NAND_STATUS_READY	0x40
+#define NAND_STATUS_WP		0x80
+
+/*
+ * Constants for ECC_MODES
+ */
+
+/* No ECC. Usage is not recommended ! */
+#define NAND_ECC_NONE		0
+/* Software ECC 3 byte ECC per 256 Byte data */
+#define NAND_ECC_SOFT		1
+/* Hardware ECC 3 byte ECC per 256 Byte data */
+#define NAND_ECC_HW3_256	2
+/* Hardware ECC 3 byte ECC per 512 Byte data */
+#define NAND_ECC_HW3_512	3
+/* Hardware ECC 6 byte ECC per 512 Byte data */
+#define NAND_ECC_HW6_512	4
+/* Hardware ECC 8 byte ECC per 512 Byte data */
+#define NAND_ECC_HW8_512	6
+/* Hardware ECC 12 byte ECC per 2048 Byte data */
+#define NAND_ECC_HW12_2048	7
+
+/*
+ * Constants for Hardware ECC
+*/
+/* Reset Hardware ECC for read */
+#define NAND_ECC_READ		0
+/* Reset Hardware ECC for write */
+#define NAND_ECC_WRITE		1
+/* Enable Hardware ECC before syndrom is read back from flash */
+#define NAND_ECC_READSYN	2
+
+/* Option constants for bizarre disfunctionality and real
+*  features
+*/
+/* Chip can not auto increment pages */
+#define NAND_NO_AUTOINCR	0x00000001
+/* Buswitdh is 16 bit */
+#define NAND_BUSWIDTH_16	0x00000002
+/* Device supports partial programming without padding */
+#define NAND_NO_PADDING		0x00000004
+/* Chip has cache program function */
+#define NAND_CACHEPRG		0x00000008
+/* Chip has copy back function */
+#define NAND_COPYBACK		0x00000010
+/* AND Chip which has 4 banks and a confusing page / block
+ * assignment. See Renesas datasheet for further information */
+#define NAND_IS_AND		0x00000020
+/* Chip has a array of 4 pages which can be read without
+ * additional ready /busy waits */
+#define NAND_4PAGE_ARRAY	0x00000040
+
+/* Options valid for Samsung large page devices */
+#define NAND_SAMSUNG_LP_OPTIONS \
+	(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
+
+/* Macros to identify the above */
+#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
+#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
+#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
+#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
+
+/* Mask to zero out the chip options, which come from the id table */
+#define NAND_CHIPOPTIONS_MSK	(0x0000ffff & ~NAND_NO_AUTOINCR)
+
+/* Non chip related options */
+/* Use a flash based bad block table. This option is passed to the
+ * default bad block table function. */
+#define NAND_USE_FLASH_BBT	0x00010000
+/* The hw ecc generator provides a syndrome instead a ecc value on read
+ * This can only work if we have the ecc bytes directly behind the
+ * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
+#define NAND_HWECC_SYNDROME	0x00020000
+
+
+/* Options set by nand scan */
+/* Nand scan has allocated oob_buf */
+#define NAND_OOBBUF_ALLOC	0x40000000
+/* Nand scan has allocated data_buf */
+#define NAND_DATABUF_ALLOC	0x80000000
+
+
+/*
+ * nand_state_t - chip states
+ * Enumeration for NAND flash chip state
+ */
+typedef enum {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING,
+	FL_CACHEDPRG,
+} nand_state_t;
+
+/* Keep gcc happy */
+struct nand_chip;
+
+#if 0
+/**
+ * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
+ * @lock:		protection lock
+ * @active:		the mtd device which holds the controller currently
+ */
+struct nand_hw_control {
+	spinlock_t	 lock;
+	struct nand_chip *active;
+};
+#endif
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA	0x98
+#define NAND_MFR_SAMSUNG	0xec
+#define NAND_MFR_FUJITSU	0x04
+#define NAND_MFR_NATIONAL	0x8f
+#define NAND_MFR_RENESAS	0x07
+#define NAND_MFR_STMICRO	0x20
+#define NAND_MFR_MICRON		0x2c
+
+/**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
+ *
+ * @name:	Identify the device type
+ * @id:		device ID code
+ * @pagesize:	Pagesize in bytes. Either 256 or 512 or 0
+ *		If the pagesize is 0, then the real pagesize
+ *		and the eraseize are determined from the
+ *		extended id bytes in the chip
+ * @erasesize:	Size of an erase block in the flash device.
+ * @chipsize:	Total chipsize in Mega Bytes
+ * @options:	Bitfield to store chip relevant options
+ */
+struct nand_flash_dev {
+	char *name;
+	int id;
+	unsigned long pagesize;
+	unsigned long chipsize;
+	unsigned long erasesize;
+	unsigned long options;
+};
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @name:	Manufacturer name
+ * @id:		manufacturer ID code of device.
+*/
+struct nand_manufacturers {
+	int id;
+	char * name;
+};
+
+extern struct nand_flash_dev nand_flash_ids[];
+extern struct nand_manufacturers nand_manuf_ids[];
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK	0x0000000F
+#define NAND_BBT_1BIT		0x00000001
+#define NAND_BBT_2BIT		0x00000002
+#define NAND_BBT_4BIT		0x00000004
+#define NAND_BBT_8BIT		0x00000008
+/* The bad block table is in the last good block of the device */
+#define NAND_BBT_LASTBLOCK	0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE	0x00000020
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_SEARCH		0x00000040
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP	0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION	0x00000100
+/* Create a bbt if none axists */
+#define NAND_BBT_CREATE		0x00000200
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES	0x00000400
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY	0x00000800
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE		0x00001000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT	0x00002000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE	0x00004000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS 4
+
+/*
+* Constants for oob configuration
+*/
+#define NAND_SMALL_BADBLOCK_POS		5
+#define NAND_LARGE_BADBLOCK_POS		0
+
+#endif /* __LINUX_MTD_NAND_H */

Property changes on: firmware/target/arm/as352x/nand.h
___________________________________________________________________
Name: svn:eol-style
 +native
Name: svn:executable
 +*
Name: svn:keywords
 +"HeadURL Id LastChangedBy LastChangedDate LastChangedRevision"
Name: svn:mime-type
 +text/x-c++hdr

=== firmware/target/arm/as352x/system-as352x.c
==================================================================
--- firmware/target/arm/as352x/system-as352x.c	(revision 16933)
+++ firmware/target/arm/as352x/system-as352x.c	(patch as352x level 1)
@@ -0,0 +1,471 @@
+/*
+* Copyright (C) 2006 Austriamicrosystems Corporation
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+/*#include <common.h>*/
+/* Prefer local inttypes.h to system */
+#include "inttypes.h"
+#include "as352x.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Macro introduced to compensate for no support for floating point
+division operation in the processor. So to get the correct value,
+roundup is peformed to provide accurate results for certain conditions.
+*/
+
+#define DIVIDE_AND_ROUND_UP(dividend,divisor) \
+ ( ( (dividend) + (divisor) - 1 ) / (divisor) )
+
+/* For sake of completness and for easier exchanging of round-up and
+round-down
+divisions provide also a round-down macro */
+
+#define DIVIDE_AND_ROUND_DOWN( a , b ) ((a)/(b))
+
+/* Macro which evaluates to the absolute value of an integer value*/
+#define ABS(A) (((A)>0)?(A):(-(A)))
+
+/* ------------------------defines for Dynamic Mem--------------------------- */
+#define AS352X_SDRAM_BASE_ADDR(offset) (0xc6030000 + offset)
+
+#define AS352X_MPMC_CONTROL  AS352X_SDRAM_BASE_ADDR( 0x00 )
+#define AS352X_MPMC_CONFIG   AS352X_SDRAM_BASE_ADDR( 0x08 )
+#define AS352X_MPMC_DYRDCFG  AS352X_SDRAM_BASE_ADDR( 0x28 )
+#define AS352X_MPMC_DYTRP    AS352X_SDRAM_BASE_ADDR( 0x30 )
+#define AS352X_MPMC_DYTRAS   AS352X_SDRAM_BASE_ADDR( 0x34 )
+#define AS352X_MPMC_DYTSREX  AS352X_SDRAM_BASE_ADDR( 0x38 )
+#define AS352X_MPMC_DYTAPR   AS352X_SDRAM_BASE_ADDR( 0x3C )
+#define AS352X_MPMC_DYTDAL   AS352X_SDRAM_BASE_ADDR( 0x40 )
+#define AS352X_MPMC_DYTWR    AS352X_SDRAM_BASE_ADDR( 0x44 )
+#define AS352X_MPMC_DYTRC    AS352X_SDRAM_BASE_ADDR( 0x48 )
+#define AS352X_MPMC_DYTRFC   AS352X_SDRAM_BASE_ADDR( 0x4C )
+#define AS352X_MPMC_DYTXSR   AS352X_SDRAM_BASE_ADDR( 0x50 )
+#define AS352X_MPMC_DYTRRD   AS352X_SDRAM_BASE_ADDR( 0x54 )
+#define AS352X_MPMC_DYTMRD   AS352X_SDRAM_BASE_ADDR( 0x58 )
+#define AS352X_MPMC_DYRASCAS0 AS352X_SDRAM_BASE_ADDR( 0x104  )
+#define AS352X_MPMC_DYCONFIG0 AS352X_SDRAM_BASE_ADDR( 0x100  )
+#define AS352X_MPMC_DYCNTL    AS352X_SDRAM_BASE_ADDR( 0x20  )
+#define AS352X_MPMC_DYREF     AS352X_SDRAM_BASE_ADDR( 0x24  )
+
+
+#define MPMC_CLK_IN_MHZ_MIN        20
+#define MPMC_1_CLKCYCLE_IN_NS_MIN  50
+
+/* TODO: If we clock down system for power management,
+ *       MPMC_CLK may be affected as well.
+ *       So either make sure MPMC clock is kept constant after init,
+ *       or use global variable (uint8_t should be enough) 
+ *       for MPMC_CLK_IN_MHZ or MPMC_1_CLKCYCLE_IN_NS (or both).
+ */
+#if 1
+#define MPMC_CLK_IN_MHZ       66
+#else
+#define MPMC_CLK_IN_MHZ       24
+#endif
+
+#if   MPMC_CLK_IN_MHZ == 24
+#define MPMC_1_CLKCYCLE_IN_NS 42
+#elif MPMC_CLK_IN_MHZ == 66
+#define MPMC_1_CLKCYCLE_IN_NS 16
+#else
+#define MPMC_1_CLKCYCLE_IN_NS 16
+#endif
+
+
+#if defined(SANSA_E200_V2)
+/*
+ * Sandisk Sansa E200v2 uses
+ * Samsung K4S641632K-TL75
+ * 4Mbx16 = 64Mbit SDRAM, max freq: 133MHz
+ */
+
+#define MPMC_DY_TRP_IN_NS       20 /* Row precharge time */
+
+#define MPMC_DY_TRAS_MIN_IN_NS  45 /* Row active time */
+#define MPMC_DY_TRAS_IN_NS      50 /* maximum is 100ns */
+#define MPMC_DY_TAPR_INNS        0 /* N/A */
+#define MPMC_SDRAM_TCK_IN_NS    10 /* ??? TODO: check */
+#define MPMC_DY_TDAL_IN_NS  ((2 * (MPMC_1_CLKCYCLE_IN_NS)) + MPMC_DY_TRP_IN_NS)
+                                   /* Last data in to active delay */
+
+#define MPMC_DY_TRDL_IN_NS      (2 * MPMC_1_CLKCYCLE_IN_NS)
+                                   /* Last data in to row precharge */
+#define MPMC_DY_TWR_IN_NS       MPMC_DY_TRDL_IN_NS
+#define MPMC_DY_TRC_IN_NS       65 /* Row cycle time */
+#define MPMC_DY_TRFC_INNS       MPMC_DY_TRC_IN_NS
+                                   /* tRC = tRFC */
+#define MPMC_DY_TXSR_IN_NS      80 /* ??? TODO: check */
+
+#define MPMC_DY_TRRD_IN_NS      20 /* Row active to row active delay */
+#define MPMC_DY_TMRD_IN_NS      (2 * (MPMC_SDRAM_TCK_IN_NS))
+                                   /* ??? TODO: check */
+
+/* Address strobe latencies in clock cycles */
+#define MPMC_SDRAM_CAS   0x3    /* to be safe;SDRAM supports CAS=2 as well */
+#define MPMC_SDRAM_RAS   0x3
+
+/* Low Power device bit settings  */
+/* Samsung - 64Mbit - standard 3.3V JEDEC,
+ * i.e. NOT Low Power
+ */
+#define MPMC_SDRAM_DEVICE_TYPE    (0   << 3)
+
+/* WARNING: This will not work!!!
+ * TODO: lookup correct Address mapping for Samsung in datasheet
+ *       Organization: 4Mb x 16,
+ *                     i.e. 16 bit high performance JEDEC SDRAM (NO low power),
+ *                     A0..A11 row address    (12 bits row length),
+ *                     A0..A7  column address ( 8 bits col length)
+ */
+#warning "MPMC_SDRAM_ADDR_MAPPING needs correction"
+#define MPMC_SDRAM_ADDR_MAPPING   (0x11 << 7)
+
+/* TREF for Samsung - 64Mbit) */
+/*64ms divided by 8192 */ /* ?!?!?! */
+#warning "MPMC_SDRAM_tREF_inNs: value does not equal (tREF[ms] * 1000)" 
+#define MPMC_SDRAM_tREF_inNs           7812
+
+#elif defined(AS352X_PBX_DEVBOARD)
+
+/* APP Board 1.0 or 2.0 */
+
+/* ------------------ MT48LC4M16A2 SDRAM & MT48LC32M16A2 SDRAM --------------------------- */
+#if 1
+#define MPMC_DY_TRP_IN_NS       20
+#else
+#define MPMC_DY_TRP_IN_NS       10
+#endif
+
+#define MPMC_DY_TRAS_MIN_IN_NS  50
+#define MPMC_DY_TRAS_IN_NS      MPMC_DY_TRAS_MIN_IN_NS
+
+/* tAPR not available for micron MT48LC4M16A2 SDRAM */
+#define MPMC_DY_TAPR_INNS  0
+
+#if 0
+#define MPMC_SDRAM_TCK_IN_NS  20
+#else
+#define MPMC_SDRAM_TCK_IN_NS  10
+#endif
+#define MPMC_DY_TDAL_IN_NS  (5 * (MPMC_SDRAM_TCK_IN_NS))
+
+/* tWR can be minimum 15ns or 1CLK * 7ns */
+#define MPMC_DY_TWR_IN_NS  (MPMC_1_CLKCYCLE_IN_NS + 8)
+#define MPMC_DY_TRC_IN_NS  70
+
+#define MPMC_DY_TRFC_INNS 70
+
+#define MPMC_DY_TXSR_IN_NS 80
+
+#define MPMC_DY_TRRD_IN_NS 20
+#define MPMC_DY_TMRD_IN_NS (2 * (MPMC_SDRAM_TCK_IN_NS))
+
+#define MPMC_SDRAM_CAS   0x2
+#define MPMC_SDRAM_RAS   0x2    /* hha??? */
+
+/* Low Power device bit settings  */
+/* Device Type for APP Board 2.0 and 1.0  */
+/* MT48LC32M16A2 - 512Mbit and MT48LC4M16 - 64Mbit -both NOT Low Power
+ * */
+#define MPMC_SDRAM_DEVICE_TYPE    (0   << 3)
+
+/* Addr Mapping for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */
+#define MPMC_SDRAM_ADDR_MAPPING   (0x11 << 7)
+
+/* TREF for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */
+/*64ms divided by 8192 */
+#define MPMC_SDRAM_tREF_inNs           7812
+
+#else /* Unknown pcb. */
+
+#error "No SDRAM timings defined for this board."
+
+#endif
+
+
+/*ROW and COLUMN size mapping for mpmc SoC device */
+
+#define MPMC_SDRAM_32BIT_EXTBUS   (0   <<14)
+#define MPMC_SDRAM_BUFFER_DISABLE (0   <<19)
+#define MPMC_SDRAM_BUFFER_ENABLE  (1   <<19)
+#define MPMC_SDRAM_WP_ENABLE      (0   <<20)
+
+#warning "Check MPMC_SDRAM_DYN_CONFIG bit by bit"
+#define MPMC_SDRAM_DYN_CONFIG ((MPMC_SDRAM_DEVICE_TYPE) | \
+ (MPMC_SDRAM_ADDR_MAPPING) | \
+ (MPMC_SDRAM_32BIT_EXTBUS) | \
+ (MPMC_SDRAM_BUFFER_DISABLE) | \
+ (MPMC_SDRAM_WP_ENABLE))
+
+#define MPMC_SDRAM_START_2_REF_CYCLES  2
+
+#warning "Check refresh time calculation"
+#define MPMC_SDRAM_DYNAMIC_REF         ((MPMC_SDRAM_tREF_inNs) / (MPMC_1_CLKCYCLE_IN_NS_MIN))
+/* CAS Latency  for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */
+#if MPMC_SDRAM_CAS == 2
+#define MPMC_SDRAM_MODEVALUE           (0x23 << 13)
+#else
+#define MPMC_SDRAM_MODEVALUE           (0x33 << 13)
+#endif
+
+
+/* ----------------------------------- functions --------------------------- */
+static inline void
+delay (unsigned long loops)
+{
+    __asm__ volatile ("1:\n"
+                      "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0" (loops));
+}
+
+void
+sdram_init (void)
+{
+    volatile uint32_t Temp;
+
+
+
+    *(volatile uint32_t *) AS352X_MPMC_CONTROL = 0x00000001;
+
+    *(volatile uint32_t *) (AS352X_MPMC_CONFIG) = 0x00000000;
+
+    *(volatile uint32_t *) (AS352X_MPMC_DYRDCFG) = 0x00000001;
+
+    /* MPMCDynamicRP setup */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTRP) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TRP_IN_NS), (MPMC_1_CLKCYCLE_IN_NS));
+
+    /* MPMCDytRAS setup */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTRAS) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TRAS_IN_NS), (MPMC_1_CLKCYCLE_IN_NS));
+
+    /* Setup MPMCDynamicSREX */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTSREX) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TXSR_IN_NS), (MPMC_1_CLKCYCLE_IN_NS));
+
+    /* Setup MPMCDynamictAPR */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTAPR) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TAPR_INNS), (MPMC_1_CLKCYCLE_IN_NS));
+
+    *(volatile uint32_t *) (AS352X_MPMC_DYTDAL) =
+        (1 +
+         (DIVIDE_AND_ROUND_UP
+          ((MPMC_DY_TDAL_IN_NS), (MPMC_1_CLKCYCLE_IN_NS))));
+
+    /* Setup MPMCDynamictWR */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTWR) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TWR_IN_NS), (MPMC_1_CLKCYCLE_IN_NS));
+
+    /* Setup MPMCDynamictRC */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTRC) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TRC_IN_NS), (MPMC_1_CLKCYCLE_IN_NS));
+
+    /* Setup MPMCDynamictRFC */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTRFC) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TRFC_INNS), (MPMC_1_CLKCYCLE_IN_NS));
+
+    /* Setup MPMCDynamictXSR */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTXSR) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TXSR_IN_NS), (MPMC_1_CLKCYCLE_IN_NS));
+
+    /* Setup MPMCDynamictRRD */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTRRD) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TRRD_IN_NS), (MPMC_1_CLKCYCLE_IN_NS));
+
+    /* Setup MPMCDynamictMRD */
+    *(volatile uint32_t *) (AS352X_MPMC_DYTMRD) =
+        DIVIDE_AND_ROUND_UP ((MPMC_DY_TMRD_IN_NS), (MPMC_1_CLKCYCLE_IN_NS));
+
+
+    *(volatile uint32_t *) (AS352X_MPMC_DYRASCAS0) =
+        ((MPMC_SDRAM_CAS << 0x8) | (MPMC_SDRAM_RAS));
+
+
+    *(volatile uint32_t *) (AS352X_MPMC_DYCONFIG0) = MPMC_SDRAM_DYN_CONFIG;
+
+    /*wait for 200uS by performing dummy read operation which
+       consumes two */
+    /* clock cycles for each operation */
+    delay (50);
+
+    *(volatile uint32_t *) (AS352X_MPMC_DYCNTL) = 0x00000183;   /* apply
+                                                                   NOP */
+
+    delay (1);
+
+    /* write to MPMCDyCntl reg to start PRECHARGing: PRECHARGE ALL
+     */
+    *(volatile uint32_t *) (AS352X_MPMC_DYCNTL) = 0x00000103;
+
+    delay (100);
+
+    /* start two auto refresh */
+    *(volatile uint32_t *) (AS352X_MPMC_DYREF) =
+        MPMC_SDRAM_START_2_REF_CYCLES;
+
+ /*- wait for 64 clk cycles of HCLK-*/
+    delay (128);
+
+    /* Program the operational value of the Refresh cycles,
+       depending upon the
+       device specified period */
+#warning "Check MPMC Dynamic Refresh register bits"
+    *(volatile uint32_t *) (AS352X_MPMC_DYREF) = MPMC_SDRAM_DYNAMIC_REF / 6;
+
+    /* Send the Mode set command to SDRAM */
+    *(volatile uint32_t *) (AS352X_MPMC_DYCNTL) = 0x00000083;
+
+
+/*----------------------------------------------------------------------*/
+
+    /* Read the SDRAM address with the mode value, such that SDRAM
+       will be
+       selected and the mode value will go as row address in HADDR
+       [23:12] */
+    Temp = *(volatile uint32_t *) (0x30000000 + MPMC_SDRAM_MODEVALUE);
+
+    /*  Merged with S.U. */
+#ifdef SDRAM_MT48H8M16LF
+    /* Device Type for APP Board 2.0 (MT48H8M16LF   - 128Mbit - Low
+       Power) */
+    /* Read the SDRAM address with the mode value, such that SDRAM
+       will be
+       selected and the mode value will go as row address in HADDR
+       [23:12] */
+    Temp = *(volatile uint32_t *) (0x30000000 + MPMC_SDRAM_EXMODEVALUE);
+#endif /*SDRAM_MT48H8M16LF */
+
+
+/*----------------------------------------------------------------------*/
+    /* Send the Normal mode set command to the SDRAM */
+    *(volatile uint32_t *) (AS352X_MPMC_DYCNTL) = 0x00000003;
+
+    /* Enable the buffer for the SDRAM */
+    Temp = *(volatile uint32_t *) (AS352X_MPMC_DYCONFIG0);
+    *(volatile uint32_t *) (AS352X_MPMC_DYCONFIG0) =
+        Temp | (MPMC_SDRAM_BUFFER_ENABLE);
+
+}
+
+#define CCU_COUNT_MIN_10_MICROSEC 640
+/*
+* Miscellaneous platform dependent initialisations
+*/
+
+void
+ccu_reset_device (uint32_t deviceMask)
+{
+    int i;
+
+    /* reset devices */
+    wreg32 (CCU_SRC, deviceMask);
+    wreg32 (CCU_SRL, CCU_SRL_MAGIC_NUMBER);
+
+    /* hold the reset for at least 10 microseconds */
+    for (i = CCU_COUNT_MIN_10_MICROSEC; i > 0; i--)
+      {
+          wreg32 (CCU_SRL, CCU_SRL_MAGIC_NUMBER);
+      }
+
+    /* remove lock */
+    wreg32 (CCU_SRL, 0);
+    wreg32 (CCU_SRC, 0);
+}
+
+void
+clk_set_async_mode (void)
+{
+    unsigned long i;
+    /* read CP15 register 1 into r0 */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /*enable asynchronous clocking mode */
+    asm ("orr r0, %0, #(0x3 <<30) ": :"r" (i));
+    /* write cp15 register 1 */
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+
+int
+board_init (void)
+{
+    ccu_reset_device (CCU_RESET_ALL_BUT_MEMORY);
+
+    wreg32 (CGU_REG_PERI, 0x0F802000);
+    wreg32 (CGU_REG_PROC, 0);
+    wreg32 (CGU_REG_AUDIO, 0);
+    wreg32 (CGU_REG_USB, 0);
+    wreg32 (CGU_REG_INTCTRL, 0);
+
+    wreg32 (CGU_REG_COUNTA, 0);
+    wreg32 (CGU_REG_COUNTB, 0);
+    wreg32 (CGU_REG_IDE, 0);
+    wreg32 (CGU_REG_MEMSTICK, 0);
+    wreg32 (CGU_REG_DBOP, 0);
+
+
+    wreg32 (CGU_REG_PLLASUP, 0x8);
+    wreg32 (CGU_REG_PLLBSUP, 0x8);
+
+    wreg32 (CGU_REG_PLLA, 0);
+    wreg32 (CGU_REG_PLLB, 0);
+
+    clk_set_async_mode ();
+    //set cpu and bus default clock
+    //plla 384M, CPU 192M,mpmc 64M,pclk 64M
+
+    wreg32 (CGU_REG_PLLA, 0x2630);
+    wreg32 (CGU_REG_PLLASUP, 0);
+    wreg32 (CGU_REG_COUNTA, CGU_LOCK_CNT);
+    while (!(rreg32 (CGU_REG_INTCTRL) & 1));
+
+    wreg32 (CGU_REG_PROC, 0x011);
+    wreg32 (CGU_REG_PERI, 0x0EF2E295);
+
+
+
+    //ccuResetDevice( CCU_RESET_ALL_BUT_MEMORY );
+
+#if 0
+    /* arch number of AS352X-Board */
+    gd->bd->bi_arch_number = MACH_TYPE_AS352X;
+
+    /* adress of boot parameters */
+    gd->bd->bi_boot_params = 0x30000100;
+#endif
+
+    sdram_init ();
+
+    return 0;
+}
+
+int
+dram_init (void)
+{
+/*
+    gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+    gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+*/
+
+    return 0;
+}
+
+#error "To prevent malfunction of your device,"
+#error "all warnings have to be addressed before flashing."

Property changes on: firmware/target/arm/as352x/system-as352x.c
___________________________________________________________________
Name: svn:eol-style
 +native
Name: svn:keywords
 +"HeadURL Id LastChangedBy LastChangedDate LastChangedRevision"
Name: svn:mime-type
 +text/x-csrc

=== firmware/target/arm/as352x/crt0.S
==================================================================
--- firmware/target/arm/as352x/crt0.S	(revision 16933)
+++ firmware/target/arm/as352x/crt0.S	(patch as352x level 1)
@@ -0,0 +1,378 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Austria Microsystems
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "cpu.h"
+
+.section .init.text."ax".%progbits
+
+/*************************************************************************
+ *
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *
+ *************************************************************************/
+
+.global start
+
+start:
+    b reset
+    ldr pc, _undefined_instruction
+    ldr pc, _software_interrupt
+    ldr pc, _prefetch_abort
+    ldr pc, _data_abort
+    ldr pc, _not_used
+    ldr pc, _irq
+    ldr pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:    .word software_interrupt
+_prefetch_abort:        .word prefetch_abort
+_data_abort:            .word data_abort
+_not_used:              .word not_used
+_irq:                   .word irq
+_fiq:                   .word fiq
+
+.balign 16,0xdeadbeef
+
+    /* TODO: These need to be put somewhere else and adjusted correctly
+     *
+     */
+    #warning "Remove and adjust global config symbols from crt0.S"
+    .equ CONFIG_STACKSIZE,   0x00004000
+    .equ CFG_GBL_DATA_SIZE,  0x00100000
+    .equ CFG_MALLOC_LEN,     0x00200000
+
+    /* CP15 - C1 = Register 1 - Control register */
+    .equ C1_MMU_ENABLE,   0x00000001 /* bit   0  M-Bit - MMU enable     */
+    .equ C1_D_CACHE,      0x00000004 /* bit   2  C-Bit - D-Cache enable */
+    .equ C1_I_CACHE,      0x00001000 /* bit  12  I-Bit - I-Cache enable */
+    .equ C1_NF,           0x40000000 /* bit  30 nF-Bit - not Fastbus select */
+    .equ C1_IA,           0x80000000 /* bit  31 iA-Bit - Asynchronos clock select */
+    /* C1 - Clocking modes */
+    .equ C1_CLKM_FASTBUS, 0x00000000    /* FastBus mode */
+    .equ C1_CLKM_SYNC,    C1_NF         /* Synchronous */
+    .equ C1_CLKM_RESERVED,C1_IA         /* reserved */
+    .equ C1_CLKM_ASYNC,   (C1_NF+C1_IA) /* Asynchronous */
+    .equ C1_CLKM_MASK,    (C1_NF+C1_IA)
+
+    /* CPSR - Current program status register */
+    .equ CPSR_CPUM_SVC_32,    0x00000013
+    .equ CPSR_CPUM_MASK,      0x0000001f
+    .equ CPSR_THUMB_INSTR,    0x00000020
+    .equ CPSR_FIQ_DISABLE,    0x00000040
+    .equ CPSR_IRQ_DISABLE,    0x00000080
+
+/*************************************************************************
+ *
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *
+ *************************************************************************/
+RAM_END:
+    .word 0x50000
+
+.globl _armboot_start
+_armboot_start:
+    .word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+    .word __bss_start
+
+.globl _bss_end
+_bss_end:
+    .word _end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+    .word _end+200
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+    .word _end+400
+#endif
+
+/*
+ * the actual reset code
+ */
+
+reset:
+    /* set the cpu to SVC32 mode
+     */
+    mrs r0,cpsr
+    bic r0,r0,#CPSR_CPUM_MASK /* clear out cpu mode bits [0..4] */
+    orr r0,r0,#CPSR_CPUM_SVC_32
+    orr r0,r0,#CPSR_IRQ_DISABLE
+    orr r0,r0,#CPSR_FIQ_DISABLE
+    msr cpsr,r0
+
+    /*
+     * we do sys-critical inits only at reboot,
+     * not when booting from ram!
+     */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+    bl cpu_init_crit
+#endif
+
+    /* Set up the stack
+     */
+stack_setup:
+    ldr r0, RAM_END /* upper 128 KiB: relocated uboot   */
+    sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
+    sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+    sub sp, r0, #12 /* leave 3 words for abort-stack */
+
+clear_bss:
+    ldr r0, _bss_start /* find start of bss segment */
+    ldr r1, _bss_end /* stop here */
+    mov r2, #0x00000000 /* clear */
+
+clbss_l:str r2, [r0] /* clear loop... */
+    add r0, r0, #4
+    cmp r0, r1
+    ble clbss_l
+    ldr r0,RAM_END
+    ldr r1,_bss_end
+    str r0,_armboot_start
+    add r1,r1,r0
+    str r1,_bss_end
+    ldr r1,_bss_start
+    add r1,r1,r0
+    str r1,_bss_start
+    ldr pc,_start_armboot
+
+_start_armboot: .word start_armboot
+
+
+/*************************************************************************
+ *
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *
+ *************************************************************************/
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+    mrc p15, 0, r0, c1, c0, 0 /* read CP15 register */
+    bic r0,r0, #C1_MMU_ENABLE /* disable mmu */
+    bic r0,r0, #C1_D_CACHE    /* disable d-cache */
+    bic r0,r0, #C1_I_CACHE    /* disable i-cache */
+    bic r0,r0, #C1_CLKM_MASK  /* select fastbus mode */
+    mcr p15, 0, r0, c1, c0, 0 /* write value back */
+
+    /* invalidate all caches to have a clean startup */
+    mov r2, #0
+    mcr p15, 0, r2, c7, c7, 0 /* Invalidate D- and I-Cache */
+    mcr p15, 0, r2, c8, c7, 0 /* Invalidate all TLBs */
+
+    /*
+     * before relocating, we have to setup RAM timing
+     * because memory timing is board-dependend, you will
+     * find a lowlevel_init.S in your board directory.
+     */
+    mov ip, lr
+    bl lowlevel_init
+    mov lr, ip
+    mov pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*************************************************************************
+ *
+ *
+ * Interrupt handling
+ *
+ *
+ *************************************************************************/
+
+/*
+ * IRQ stack frame.
+ */
+.equ S_FRAME_SIZE, 72
+
+.equ S_OLD_R0, 68
+.equ S_PSR,    64
+.equ S_PC,     60
+.equ S_LR,     56
+.equ S_SP,     52
+
+.equ S_IP,     48
+.equ S_FP,     44
+.equ S_R10,    40
+.equ S_R9,     36
+.equ S_R8,     32
+.equ S_R7,     28
+.equ S_R6,     24
+.equ S_R5,     20
+.equ S_R4,     16
+.equ S_R3,     12
+.equ S_R2,      8
+.equ S_R1,      4
+.equ S_R0,      0
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+.macro bad_save_user_regs
+    sub sp, sp, #S_FRAME_SIZE
+    stmia sp, {r0 - r12} /* Calling r0-r12 */
+    ldr r2, _armboot_start
+    sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+    sub r2, r2, #CFG_GBL_DATA_SIZE
+    sub r2, r2, #8  /* set base 2 words into abort stack */
+    ldmia r2, {r2 - r3} /* get pc, cpsr */
+    add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
+
+    add r5, sp, #S_SP
+    mov r1, lr
+    stmia r5, {r0 - r3} /* save sp_SVC, lr_SVC, pc, cpsr */
+    mov r0, sp
+.endm
+
+.macro irq_save_user_regs
+    sub sp, sp, #S_FRAME_SIZE
+    stmia sp, {r0 - r12} /* Calling r0-r12 */
+    add     r8, sp, #S_PC
+    stmdb   r8, {sp, lr}^                   /* Calling SP, LR */
+    str     lr, [r8, #0]                    /* Save calling PC */
+    mrs     r6, spsr
+    str     r6, [r8, #4]                    /* Save CPSR */
+    str     r0, [r8, #8]                    /* Save OLD_R0 */
+    mov r0, sp
+.endm
+
+.macro irq_restore_user_regs
+    ldmia sp, {r0 - lr}^ /* Calling r0 - lr */
+    mov r0, r0
+    ldr lr, [sp, #S_PC] /* Get PC */
+    add sp, sp, #S_FRAME_SIZE
+    subs pc, lr, #4 /* return & move spsr_svc into cpsr */
+.endm
+
+.macro get_bad_stack
+    ldr r13, _armboot_start /* setup our mode stack */
+    sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+    sub r13, r13, #CFG_GBL_DATA_SIZE
+    sub r13, r13, #8 /* reserved a couple spots in abort stack */
+
+    str lr, [r13] /* save caller lr / spsr */
+    mrs lr, spsr
+    str     lr, [r13, #4]
+
+    mov r13, #CPSR_CPUM_SVC_32 /* prepare SVC-Mode */
+#if 0
+    msr spsr_c, r13
+#endif
+    msr spsr, r13
+    mov lr, pc
+    movs pc, lr
+.endm
+
+.macro get_irq_stack @ setup IRQ stack
+    ldr sp, IRQ_STACK_START
+.endm
+
+.macro get_fiq_stack @ setup FIQ stack
+    ldr sp, FIQ_STACK_START
+.endm
+
+/*
+ * exception handlers
+ */
+.align  5
+undefined_instruction:
+    get_bad_stack
+    bad_save_user_regs
+    bl do_undefined_instruction
+
+.align 5
+software_interrupt:
+    get_bad_stack
+    bad_save_user_regs
+    bl do_software_interrupt
+
+.align 5
+prefetch_abort:
+    get_bad_stack
+    bad_save_user_regs
+    bl do_prefetch_abort
+
+.align 5
+data_abort:
+    get_bad_stack
+    bad_save_user_regs
+    bl do_data_abort
+
+.align 5
+not_used:
+    get_bad_stack
+    bad_save_user_regs
+    bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+.align 5
+irq:
+    get_irq_stack
+    irq_save_user_regs
+    bl do_irq
+    irq_restore_user_regs
+
+.align 5
+fiq:
+    get_fiq_stack
+    /* someone ought to write a more effiction fiq_save_user_regs */
+    irq_save_user_regs
+    bl do_fiq
+    irq_restore_user_regs
+
+#else
+
+.align 5
+irq:
+    get_bad_stack
+    bad_save_user_regs
+    bl do_irq
+
+.align 5
+fiq:
+    get_bad_stack
+    bad_save_user_regs
+    bl do_fiq
+
+#endif
+
=== firmware/target/arm/interrupts-arm922t.c
==================================================================
--- firmware/target/arm/interrupts-arm922t.c	(revision 16933)
+++ firmware/target/arm/interrupts-arm922t.c	(patch as352x level 1)
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@...>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@...>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@...>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm920t.h>
+#include <asm/proc-armv/ptrace.h>
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+     "bic %0, %0, #0x80\n"
+     "msr cpsr_c, %0"
+     : "=r" (temp)
+     :
+     : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+ unsigned long old,temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+     "orr %1, %0, #0xc0\n"
+     "msr cpsr_c, %1"
+     : "=r" (old), "=r" (temp)
+     :
+     : "memory");
+ return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+ panic ("Resetting CPU ...\n");
+ reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+ unsigned long flags;
+ const char *processor_modes[] = {
+ "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
+ "UK4_26", "UK5_26", "UK6_26", "UK7_26",
+ "UK8_26", "UK9_26", "UK10_26", "UK11_26",
+ "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
+ "UK4_32", "UK5_32", "UK6_32", "ABT_32",
+ "UK8_32", "UK9_32", "UK10_32", "UND_32",
+ "UK12_32", "UK13_32", "UK14_32", "SYS_32",
+ };
+
+ flags = condition_codes (regs);
+
+ printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
+ "sp : %08lx  ip : %08lx  fp : %08lx\n",
+ instruction_pointer (regs),
+ regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+ printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+ printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+ printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+ printf ("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' :
+'v');
+ printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
+ interrupts_enabled (regs) ? "on" : "off",
+ fast_interrupts_enabled (regs) ? "on" : "off",
+ processor_modes[processor_mode (regs)],
+ thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+ printf ("undefined instruction\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+ printf ("software interrupt\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+ printf ("prefetch abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+ printf ("data abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+ printf ("not used\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+ printf ("fast interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+ printf ("interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}

Property changes on: firmware/target/arm/interrupts-arm922t.c
___________________________________________________________________
Name: svn:eol-style
 +native
Name: svn:keywords
 +"HeadURL Id LastChangedBy LastChangedDate LastChangedRevision"
Name: svn:mime-type
 +text/x-csrc

=== firmware/drivers/rtc/rtc_as3514.c
==================================================================
--- firmware/drivers/rtc/rtc_as3514.c	(revision 16933)
+++ firmware/drivers/rtc/rtc_as3514.c	(patch as352x level 1)
@@ -159,9 +159,13 @@
             + year_days*DAY_SECONDS;
 
     /* Send data to RTC */
+#ifdef CPU_PP
     for (i=0;i<4;i++){
         pp_i2c_send(AS3514_I2C_ADDR, RTC_0 + i, ((seconds >> (8 * i)) & 0xff));
     }
+#else
+    
+#endif
     return 1;
 }
 
=== firmware/drivers/audio/as3514.c
==================================================================
--- firmware/drivers/audio/as3514.c	(revision 16933)
+++ firmware/drivers/audio/as3514.c	(patch as352x level 1)
@@ -132,6 +132,7 @@
 {
     unsigned int i;
 
+#ifdef CPU_PP
     /* normal outputs for CDI and I2S pin groups */
     DEV_INIT2 &= ~0x300;
 
@@ -156,6 +157,12 @@
     /* external dev clock to 24MHz */
     outl(inl(0x70000018) & ~0xc, 0x70000018);
 
+#elif defined(CPU_AS352X)
+
+    /* TODO: I2C initialization for AS352X (if needed) */
+
+#endif
+
     i2s_reset();
 
     /* Set ADC off, mixer on, DAC on, line out off, line in off, mic off */