Index: apps/debug_menu.c =================================================================== --- apps/debug_menu.c (revision 19983) +++ apps/debug_menu.c (working copy) @@ -2028,7 +2028,7 @@ simplelist_addline(SIMPLELIST_ADD_LINE, "No timing info"); } -#if defined (TOSHIBA_GIGABEAT_F) || defined (TOSHIBA_GIGABEAT_S) +#if defined (TOSHIBA_GIGABEAT_F) || defined (TOSHIBA_GIGABEAT_S) || defined (HAVE_ATA_DMA) if (identify_info[63] & (1<<0)) { char mdma0[2], mdma1[2], mdma2[2]; mdma0[1] = mdma1[1] = mdma2[1] = 0; @@ -2046,18 +2046,19 @@ simplelist_addline(SIMPLELIST_ADD_LINE, "No MDMA mode info"); } - if (identify_info[88] & (1<<0)) { - char udma0[2], udma1[2], udma2[2], udma3[2], udma4[2], udma5[2]; - udma0[1] = udma1[1] = udma2[1] = udma3[1] = udma4[1] = udma5[1] = 0; + if (identify_info[53] & (1<<2)) { + char udma0[2], udma1[2], udma2[2], udma3[2], udma4[2], udma5[2], udma6[2]; + udma0[1] = udma1[1] = udma2[1] = udma3[1] = udma4[1] = udma5[1] = udma6[1] = 0; udma0[0] = (identify_info[88] & (1<<0)) ? '0' : 0; udma1[0] = (identify_info[88] & (1<<1)) ? '1' : 0; udma2[0] = (identify_info[88] & (1<<2)) ? '2' : 0; udma3[0] = (identify_info[88] & (1<<3)) ? '3' : 0; udma4[0] = (identify_info[88] & (1<<4)) ? '4' : 0; udma5[0] = (identify_info[88] & (1<<5)) ? '5' : 0; + udma6[0] = (identify_info[88] & (1<<6)) ? '6' : 0; simplelist_addline(SIMPLELIST_ADD_LINE, - "UDMA modes: %s %s %s %s %s %s", udma0, udma1, udma2, - udma3, udma4, udma5); + "UDMA modes: %s %s %s %s %s %s %s", udma0, udma1, udma2, + udma3, udma4, udma5, udma6); } else { simplelist_addline(SIMPLELIST_ADD_LINE, @@ -2078,6 +2079,18 @@ } simplelist_addline(SIMPLELIST_ADD_LINE, "Cluster size: %d bytes", fat_get_cluster_size(IF_MV(0))); +#ifdef HAVE_ATA_DMA + i = ata_get_dma_mode(); + if (i == 0) { + simplelist_addline(SIMPLELIST_ADD_LINE, + "DMA not enabled"); + } else { + simplelist_addline(SIMPLELIST_ADD_LINE, + "DMA mode: %s %c", + (i & 0x40) ? "UDMA" : "MDMA", + '0' + (i & 7)); + } +#endif return btn; } #else /* No SD, MMC or ATA */ Index: firmware/export/config-ipodvideo.h =================================================================== --- firmware/export/config-ipodvideo.h (revision 19983) +++ firmware/export/config-ipodvideo.h (working copy) @@ -204,4 +204,6 @@ #define IPOD_ACCESSORY_PROTOCOL #define HAVE_SERIAL +/* Define this to add support for ATA DMA */ +#define HAVE_ATA_DMA #endif Index: firmware/export/ata.h =================================================================== --- firmware/export/ata.h (revision 19983) +++ firmware/export/ata.h (working copy) @@ -60,5 +60,10 @@ long ata_last_disk_activity(void); int ata_spinup_time(void); /* ticks */ +#ifdef HAVE_ATA_DMA +/* Needed to allow updating while waiting for DMA to complete */ +extern long last_disk_activity; +int ata_get_dma_mode(void); +#endif #endif Index: firmware/target/arm/ata-target.h =================================================================== --- firmware/target/arm/ata-target.h (revision 19983) +++ firmware/target/arm/ata-target.h (working copy) @@ -82,3 +82,29 @@ void ata_enable(bool on); bool ata_is_coldstart(void); void ata_device_init(void); + +#ifdef HAVE_ATA_DMA + +/* IDE DMA controller registers */ +#define IDE_DMA_CONTROL (*(volatile unsigned long *)(0xc3000400)) +#define IDE_DMA_LENGTH (*(volatile unsigned long *)(0xc3000408)) +#define IDE_DMA_ADDR (*(volatile unsigned long *)(0xc300040C)) + +/* Maximum multi-word DMA mode supported by the controller */ +#define ATA_MAX_MWDMA 2 + +#ifndef BOOTLOADER +/* The PP5020 supports UDMA 4, but it needs cpu boosting and doesn't + improve test_disk results. UDMA 2 is stable at 30 Mhz. + */ +#define ATA_MAX_UDMA 1 /* AB: UDMA 1 for 24MHz normal clock */ +#else +/* The bootloader runs at 24 Mhz and needs a slower mode */ +#define ATA_MAX_UDMA 1 +#endif + +void ata_dma_set_mode(unsigned char mode); +bool ata_dma_setup(void *addr, unsigned long bytes, bool write); +bool ata_dma_finish(void); + +#endif /* HAVE_ATA_DMA */ Index: firmware/target/arm/ata-pp5020.c =================================================================== --- firmware/target/arm/ata-pp5020.c (revision 19983) +++ firmware/target/arm/ata-pp5020.c (working copy) @@ -24,6 +24,9 @@ #include #include "system.h" #include "ata-target.h" +#ifdef HAVE_ATA_DMA +#include "ata.h" +#endif void ata_reset() { @@ -44,6 +47,13 @@ void ata_device_init() { +#ifdef HAVE_ATA_DMA + /* TODO: Is it necessary to wait for ready here? */ + IDE_DMA_CONTROL |= 2; + IDE_DMA_CONTROL &= ~1; + IDE0_CFG &= ~0x8010; + IDE0_CFG |= 0x20; +#else /* From ipod-ide.c:ipod_ide_register() */ IDE0_CFG |= (1<<5); #ifdef IPOD_NANO @@ -51,7 +61,163 @@ #else IDE0_CFG &=~(0x10000000); /* cpu < 65MHz */ #endif +#endif IDE0_PRI_TIMING0 = 0x10; IDE0_PRI_TIMING1 = 0x80002150; } + +/* These are PIO timings for 80 Mhz. At 24 Mhz, + the first value is 0 but the rest are the same. + They go in IDE0_PRI_TIMING0. + + Rockbox used 0x10, and test_disk shows that leads to faster PIO. + If 0x10 is incorrect, these timings may be needed with some devices. +static const unsigned long pio80mhz[] = { + 0xC293, 0x43A2, 0x11A1, 0x7232, 0x3131 +}; +*/ + +#ifdef HAVE_ATA_DMA +/* Timings for multi-word and ultra DMA modes. + These go in IDE0_PRI_TIMING1 + */ +static const unsigned long tm_mwdma[] = { + 0xF9F92, 0x56562, 0x45451 +}; + +static const unsigned long tm_udma[] = { + 0x800037C1, 0x80003491, 0x80003371, +#if ATA_MAX_UDMA > 2 + 0x80003271, 0x80003071 +#endif +}; + +#if ATA_MAX_UDMA > 2 +static bool dma_boosted = false; +static bool dma_needs_boost; +#endif + +/* This function sets up registers for 80 Mhz. + Ultra DMA mode 2 works at 30 Mhz. + */ +void ata_dma_set_mode(unsigned char mode) { + int modeidx; + + (*(volatile unsigned long *)(0x600060C4)) = 0xC0000000; /* 80 Mhz */ + IDE0_CFG &= ~0x10000000; + + modeidx = mode & 7; + mode &= 0xF8; + if (mode == 0x40 && modeidx <= ATA_MAX_UDMA) { + IDE0_PRI_TIMING1 = tm_udma[modeidx]; +#if ATA_MAX_UDMA > 2 + if (modeidx > 2) + dma_needs_boost = true; + else + dma_needs_boost = false; +#endif + } else if (mode == 0x20 && modeidx <= ATA_MAX_MWDMA) + IDE0_PRI_TIMING1 = tm_mwdma[modeidx]; + + IDE0_CFG |= 0x20000000; /* >= 50 Mhz */ +} + +#define IDE_CFG_INTRQ 8 +#define IDE_DMA_CONTROL_READ 8 + +/* This waits for an ATA interrupt using polling. + In ATA_CONTROL, CONTROL_nIEN must be cleared. + */ +STATICIRAM ICODE_ATTR int ata_wait_intrq(void) +{ + long timeout = current_tick + HZ*10; + + do + { + if (IDE0_CFG & IDE_CFG_INTRQ) + return 1; + last_disk_activity = current_tick; + yield(); + } while (TIME_BEFORE(current_tick, timeout)); + + return 0; /* timeout */ +} + +/* This function checks if parameters are appropriate for DMA, + and if they are, it sets up for DMA. + + If return value is false, caller may use PIO for this transfer. + + If return value is true, caller must issue a DMA ATA command + and then call ata_dma_finish(). + */ +bool ata_dma_setup(void *addr, unsigned long bytes, bool write) { + if (bytes <= 512 || ((unsigned long)addr & 3)) + return false; + +#if ATA_MAX_UDMA > 2 + if (dma_needs_boost && !dma_boosted) { + cpu_boost(true); + dma_boosted = true; + } +#endif + + /* Clear pending interrupts so ata_dma_finish() can wait for an + interrupt from this transfer + */ + IDE0_CFG |= IDE_CFG_INTRQ; + + IDE_DMA_CONTROL |= 2; + IDE_DMA_LENGTH = bytes - 4; + +#ifndef BOOTLOADER + if ((unsigned long)addr < DRAM_START) + /* Rockbox remaps DRAM to start at 0 */ + IDE_DMA_ADDR = (unsigned long)addr + DRAM_START; + else +#endif + IDE_DMA_ADDR = (unsigned long)addr; + + if (write) + IDE_DMA_CONTROL &= ~IDE_DMA_CONTROL_READ; + else + IDE_DMA_CONTROL |= IDE_DMA_CONTROL_READ; + + IDE0_CFG |= 0x8000; + + return true; +} + +/* This function waits for a DMA transfer to end. + It must be called to finish what ata_dma_setup started. + + Return value is true if DMA completed before the timeout, and false + if a timeout happened. + */ +bool ata_dma_finish(void) { + bool res; + + /* It may be okay to put this at the end of setup */ + IDE_DMA_CONTROL |= 1; + + /* Wait for end of transfer. + Reading standard ATA status while DMA is in progress causes + failures and hangs. Because of that, another wait is used. + */ + res = ata_wait_intrq(); + + IDE0_CFG &= ~0x8000; + IDE_DMA_CONTROL &= ~0x80000001; + +#if ATA_MAX_UDMA > 2 + if (dma_boosted) { + cpu_boost(false); + dma_boosted = false; + } +#endif + + return res; +} + +#endif /* HAVE_ATA_DMA */ Index: firmware/drivers/ata.c =================================================================== --- firmware/drivers/ata.c (revision 19983) +++ firmware/drivers/ata.c (working copy) @@ -60,6 +60,12 @@ #define CMD_SLEEP 0xE6 #define CMD_SET_FEATURES 0xEF #define CMD_SECURITY_FREEZE_LOCK 0xF5 +#ifdef HAVE_ATA_DMA +#define CMD_READ_DMA 0xC8 +#define CMD_READ_DMA_EXT 0x25 +#define CMD_WRITE_DMA 0xCA +#define CMD_WRITE_DMA_EXT 0x35 +#endif /* Should all be < 0x100 (which are reserved for control messages) */ #define Q_SLEEP 0 @@ -169,7 +175,12 @@ static bool initialized = false; static long last_user_activity = -1; +#ifdef HAVE_ATA_DMA +/* Needed to allow updating while waiting for DMA to complete */ +long last_disk_activity = -1; +#else static long last_disk_activity = -1; +#endif static unsigned long total_sectors; static int multisectors; /* number of supported multisectors */ @@ -188,6 +199,10 @@ static int phys_sector_mult = 1; #endif +#ifdef HAVE_ATA_DMA +static int dma_mode = 0; +#endif + static int ata_power_on(void); static int perform_soft_reset(void); static int set_multiple_mode(int sectors); @@ -240,7 +255,8 @@ { if (!wait_for_bsy()) return 0; - return (ATA_ALT_STATUS & (STATUS_RDY|STATUS_DRQ)) == STATUS_RDY; + /* See FS#9721 */ + return (ATA_ALT_STATUS & (STATUS_BSY|STATUS_RDY|STATUS_DF|STATUS_DRQ|STATUS_ERR)) == STATUS_RDY; } #if (CONFIG_LED == LED_REAL) @@ -308,6 +324,9 @@ int count; void* buf; long spinup_start; +#ifdef HAVE_ATA_DMA + bool usedma = false; +#endif #ifndef MAX_PHYS_SECTOR_SIZE #ifdef HAVE_MULTIVOLUME @@ -358,6 +377,17 @@ ret = 0; last_disk_activity = current_tick; +#ifdef HAVE_ATA_DMA + /* If DMA is supported and parameters are ok for DMA, use it */ + if (dma_mode && ata_dma_setup(inbuf, incount * SECTOR_SIZE, false)) { + usedma = true; +#ifndef HAVE_DMA_CACHE_COHERENCY + /* If unflushed, old data may overwrite new on invalidate */ + cpucache_flush(); +#endif + } +#endif + #ifdef HAVE_LBA48 if (lba48) { @@ -370,7 +400,11 @@ SET_REG(ATA_HCYL, 0); /* 47:40 */ SET_REG(ATA_HCYL, (start >> 16) & 0xff); /* 23:16 */ SET_REG(ATA_SELECT, SELECT_LBA | ata_device); +#ifdef HAVE_ATA_DMA + SET_REG(ATA_COMMAND, usedma ? CMD_READ_DMA_EXT : CMD_READ_MULTIPLE_EXT); +#else SET_REG(ATA_COMMAND, CMD_READ_MULTIPLE_EXT); +#endif } else #endif @@ -380,7 +414,11 @@ SET_REG(ATA_LCYL, (start >> 8) & 0xff); SET_REG(ATA_HCYL, (start >> 16) & 0xff); SET_REG(ATA_SELECT, ((start >> 24) & 0xf) | SELECT_LBA | ata_device); +#ifdef HAVE_ATA_DMA + SET_REG(ATA_COMMAND, usedma ? CMD_READ_DMA : CMD_READ_MULTIPLE); +#else SET_REG(ATA_COMMAND, CMD_READ_MULTIPLE); +#endif } /* wait at least 400ns between writing command and reading status */ @@ -390,6 +428,29 @@ __asm__ volatile ("nop"); __asm__ volatile ("nop"); +#ifdef HAVE_ATA_DMA + if (usedma) { + if (!ata_dma_finish()) + ret = -7; + +#ifndef HAVE_DMA_CACHE_COHERENCY + /* Invalidate cache because new data may be present in RAM */ + cpucache_invalidate(); +#endif + if (ret != 0) { + perform_soft_reset(); + goto retry; + } + + if (spinup) { + spinup_time = current_tick - spinup_start; + spinup = false; + sleeping = false; + poweroff = false; + } + } + else +#endif /* HAVE_ATA_DMA */ while (count) { int sectors; int wordcount; @@ -515,6 +576,9 @@ int i; int ret = 0; long spinup_start; +#ifdef HAVE_ATA_DMA + bool usedma = false; +#endif #ifndef MAX_PHYS_SECTOR_SIZE #ifdef HAVE_MULTIVOLUME @@ -554,6 +618,17 @@ goto error; } +#ifdef HAVE_ATA_DMA + /* If DMA is supported and parameters are ok for DMA, use it */ + if (dma_mode && ata_dma_setup((void *)buf, count * SECTOR_SIZE, true)) { + usedma = true; +#ifndef HAVE_DMA_CACHE_COHERENCY + /* If unflushed, old data may overwrite new on invalidate */ + cpucache_flush(); +#endif + } +#endif + #ifdef HAVE_LBA48 if (lba48) { @@ -566,7 +641,11 @@ SET_REG(ATA_HCYL, 0); /* 47:40 */ SET_REG(ATA_HCYL, (start >> 16) & 0xff); /* 23:16 */ SET_REG(ATA_SELECT, SELECT_LBA | ata_device); +#ifdef HAVE_ATA_DMA + SET_REG(ATA_COMMAND, usedma ? CMD_WRITE_DMA_EXT : CMD_WRITE_SECTORS_EXT); +#else SET_REG(ATA_COMMAND, CMD_WRITE_SECTORS_EXT); +#endif } else #endif @@ -576,9 +655,26 @@ SET_REG(ATA_LCYL, (start >> 8) & 0xff); SET_REG(ATA_HCYL, (start >> 16) & 0xff); SET_REG(ATA_SELECT, ((start >> 24) & 0xf) | SELECT_LBA | ata_device); +#ifdef HAVE_ATA_DMA + SET_REG(ATA_COMMAND, usedma ? CMD_WRITE_DMA : CMD_WRITE_SECTORS); +#else SET_REG(ATA_COMMAND, CMD_WRITE_SECTORS); +#endif } +#ifdef HAVE_ATA_DMA + if (usedma) { + if (!ata_dma_finish()) + ret = -7; + else if (spinup) { + spinup_time = current_tick - spinup_start; + spinup = false; + sleeping = false; + poweroff = false; + } + } + else +#endif /* HAVE_ATA_DMA */ for (i=0; i= 5us */ +#ifdef HAVE_ATA_DMA + SET_REG(ATA_CONTROL, 0); +#else SET_REG(ATA_CONTROL, CONTROL_nIEN); +#endif sleep(1); /* >2ms */ /* This little sucker can take up to 30 seconds */ @@ -1172,6 +1272,22 @@ return 0; } +#ifdef HAVE_ATA_DMA +int get_best_mode(unsigned short identword, int max, int modetype) +{ + unsigned short testbit = 1u << max; + + while (1) { + if (identword & testbit) + return max | modetype; + testbit >>= 1; + if (!testbit) + return 0; + max--; + } +} +#endif + static int set_features(void) { static struct { @@ -1184,6 +1300,9 @@ { 83, 3, 0x05, 0x80 }, /* adv. power management: lowest w/o standby */ { 83, 9, 0x42, 0x80 }, /* acoustic management: lowest noise */ { 82, 6, 0xaa, 0 }, /* enable read look-ahead */ +#ifdef HAVE_ATA_DMA + { 0, 0, 0x03, 0 }, /* DMA mode */ +#endif }; int i; int pio_mode = 2; @@ -1197,7 +1316,24 @@ /* Update the table: set highest supported pio mode that we also support */ features[0].parameter = 8 + pio_mode; + +#ifdef HAVE_ATA_DMA + if (identify_info[53] & (1<<2)) + /* Ultra DMA mode info present, find a mode */ + dma_mode = get_best_mode(identify_info[88], ATA_MAX_UDMA, 0x40); + if (!dma_mode) { + /* No UDMA mode found, try to find a multi-word DMA mode */ + dma_mode = get_best_mode(identify_info[63], ATA_MAX_MWDMA, 0x20); + features[4].id_word = 63; + } + else + features[4].id_word = 88; + + features[4].id_bit = dma_mode & 7; + features[4].parameter = dma_mode; +#endif /* HAVE_ATA_DMA */ + SET_REG(ATA_SELECT, ata_device); if (!wait_for_rdy()) { @@ -1230,6 +1366,10 @@ ata_set_pio_timings(pio_mode); #endif +#ifdef HAVE_ATA_DMA + ata_dma_set_mode(dma_mode); +#endif + return 0; } @@ -1298,6 +1438,11 @@ sleep(HZ/4); /* allow voltage to build up */ } +#ifdef HAVE_ATA_DMA + /* DMA on PP5020 requires nIEN = 0 */ + SET_REG(ATA_CONTROL, 0); +#endif + /* first try, hard reset at cold start only */ rc = init_and_check(coldstart); @@ -1444,3 +1589,11 @@ info->revision=revision; } #endif + +#ifdef HAVE_ATA_DMA +/* Returns last DMA mode as set by set_features() */ +int ata_get_dma_mode(void) +{ + return dma_mode; +} +#endif