Index: firmware/export/config-ipodvideo.h =================================================================== --- firmware/export/config-ipodvideo.h (revision 20298) +++ firmware/export/config-ipodvideo.h (working copy) @@ -213,4 +213,6 @@ #define HAVE_LCD_SHUTDOWN #endif +/* Define this to add support for ATA DMA */ +#define HAVE_ATA_DMA #endif Index: firmware/target/arm/ata-target.h =================================================================== --- firmware/target/arm/ata-target.h (revision 20298) +++ firmware/target/arm/ata-target.h (working copy) @@ -82,3 +82,29 @@ void ata_enable(bool on); bool ata_is_coldstart(void); void ata_device_init(void); + +#ifdef HAVE_ATA_DMA + +/* IDE DMA controller registers */ +#define IDE_DMA_CONTROL (*(volatile unsigned long *)(0xc3000400)) +#define IDE_DMA_LENGTH (*(volatile unsigned long *)(0xc3000408)) +#define IDE_DMA_ADDR (*(volatile unsigned long *)(0xc300040C)) + +/* Maximum multi-word DMA mode supported by the controller */ +#define ATA_MAX_MWDMA 2 + +#ifndef BOOTLOADER +/* The PP5020 supports UDMA 4, but it needs cpu boosting and doesn't + improve test_disk results. UDMA 2 is stable at 30 Mhz. + */ +#define ATA_MAX_UDMA 1 /* AB: UDMA 1 for 24MHz normal clock */ +#else +/* The bootloader runs at 24 Mhz and needs a slower mode */ +#define ATA_MAX_UDMA 1 +#endif + +void ata_dma_set_mode(unsigned char mode); +bool ata_dma_setup(void *addr, unsigned long bytes, bool write); +bool ata_dma_finish(void); + +#endif /* HAVE_ATA_DMA */ Index: firmware/target/arm/ata-pp5020.c =================================================================== --- firmware/target/arm/ata-pp5020.c (revision 20298) +++ firmware/target/arm/ata-pp5020.c (working copy) @@ -24,6 +24,9 @@ #include #include "system.h" #include "ata-target.h" +#ifdef HAVE_ATA_DMA +#include "ata.h" +#endif void ata_reset() { @@ -44,6 +47,13 @@ void ata_device_init() { +#ifdef HAVE_ATA_DMA + /* TODO: Is it necessary to wait for ready here? */ + IDE_DMA_CONTROL |= 2; + IDE_DMA_CONTROL &= ~1; + IDE0_CFG &= ~0x8010; + IDE0_CFG |= 0x20; +#else /* From ipod-ide.c:ipod_ide_register() */ IDE0_CFG |= (1<<5); #ifdef IPOD_NANO @@ -51,7 +61,174 @@ #else IDE0_CFG &=~(0x10000000); /* cpu < 65MHz */ #endif +#endif IDE0_PRI_TIMING0 = 0x10; IDE0_PRI_TIMING1 = 0x80002150; } + +/* These are PIO timings for 80 Mhz. At 24 Mhz, + the first value is 0 but the rest are the same. + They go in IDE0_PRI_TIMING0. + + Rockbox used 0x10, and test_disk shows that leads to faster PIO. + If 0x10 is incorrect, these timings may be needed with some devices. +static const unsigned long pio80mhz[] = { + 0xC293, 0x43A2, 0x11A1, 0x7232, 0x3131 +}; +*/ + +#ifdef HAVE_ATA_DMA +/* Timings for multi-word and ultra DMA modes. + These go in IDE0_PRI_TIMING1 + */ +static const unsigned long tm_mwdma[] = { + 0xF9F92, 0x56562, 0x45451 +}; + +static const unsigned long tm_udma[] = { + 0x800037C1, 0x80003491, 0x80003371, +#if ATA_MAX_UDMA > 2 + 0x80003271, 0x80003071 +#endif +}; + +#if ATA_MAX_UDMA > 2 +static bool dma_boosted = false; +static bool dma_needs_boost; +#endif + +/* This function sets up registers for 80 Mhz. + Ultra DMA mode 2 works at 30 Mhz. + */ +void ata_dma_set_mode(unsigned char mode) { + int modeidx; + + (*(volatile unsigned long *)(0x600060C4)) = 0xC0000000; /* 80 Mhz */ + IDE0_CFG &= ~0x10000000; + + modeidx = mode & 7; + mode &= 0xF8; + if (mode == 0x40 && modeidx <= ATA_MAX_UDMA) { + IDE0_PRI_TIMING1 = tm_udma[modeidx]; +#if ATA_MAX_UDMA > 2 + if (modeidx > 2) + dma_needs_boost = true; + else + dma_needs_boost = false; +#endif + } else if (mode == 0x20 && modeidx <= ATA_MAX_MWDMA) + IDE0_PRI_TIMING1 = tm_mwdma[modeidx]; + + IDE0_CFG |= 0x20000000; /* >= 50 Mhz */ +} + +#define IDE_CFG_INTRQ 8 +#define IDE_DMA_CONTROL_READ 8 + +/* This waits for an ATA interrupt using polling. + In ATA_CONTROL, CONTROL_nIEN must be cleared. + */ +STATICIRAM ICODE_ATTR int ata_wait_intrq(void) +{ + long timeout = current_tick + HZ*10; + + do + { + if (IDE0_CFG & IDE_CFG_INTRQ) + return 1; + ata_keep_active(); + yield(); + } while (TIME_BEFORE(current_tick, timeout)); + + return 0; /* timeout */ +} + +/* This function checks if parameters are appropriate for DMA, + and if they are, it sets up for DMA. + + If return value is false, caller may use PIO for this transfer. + + If return value is true, caller must issue a DMA ATA command + and then call ata_dma_finish(). + */ +bool ata_dma_setup(void *addr, unsigned long bytes, bool write) { + if (bytes <= 512 || ((unsigned long)addr & 3)) + return false; + +#if ATA_MAX_UDMA > 2 + if (dma_needs_boost && !dma_boosted) { + cpu_boost(true); + dma_boosted = true; + } +#endif + + if (write) { + /* If unflushed, old data may be written to disk */ + cpucache_flush(); + } + else { + /* Invalidate cache because new data may be present in RAM */ + cpucache_invalidate(); + /* TODO: Alignment to cache line boundaries should be performed + pre/post DMA */ + } + + /* Clear pending interrupts so ata_dma_finish() can wait for an + interrupt from this transfer + */ + IDE0_CFG |= IDE_CFG_INTRQ; + + IDE_DMA_CONTROL |= 2; + IDE_DMA_LENGTH = bytes - 4; + +#ifndef BOOTLOADER + if ((unsigned long)addr < DRAM_START) + /* Rockbox remaps DRAM to start at 0 */ + IDE_DMA_ADDR = (unsigned long)addr + DRAM_START; + else +#endif + IDE_DMA_ADDR = (unsigned long)addr; + + if (write) + IDE_DMA_CONTROL &= ~IDE_DMA_CONTROL_READ; + else + IDE_DMA_CONTROL |= IDE_DMA_CONTROL_READ; + + IDE0_CFG |= 0x8000; + + return true; +} + +/* This function waits for a DMA transfer to end. + It must be called to finish what ata_dma_setup started. + + Return value is true if DMA completed before the timeout, and false + if a timeout happened. + */ +bool ata_dma_finish(void) { + bool res; + + /* It may be okay to put this at the end of setup */ + IDE_DMA_CONTROL |= 1; + + /* Wait for end of transfer. + Reading standard ATA status while DMA is in progress causes + failures and hangs. Because of that, another wait is used. + */ + res = ata_wait_intrq(); + + IDE0_CFG &= ~0x8000; + IDE_DMA_CONTROL &= ~0x80000001; + +#if ATA_MAX_UDMA > 2 + if (dma_boosted) { + cpu_boost(false); + dma_boosted = false; + } +#endif + + return res; +} + +#endif /* HAVE_ATA_DMA */