--- firmware/target/arm/ata-pp5020.c.orig	2009-08-18 11:49:21.301400000 -0400
+++ firmware/target/arm/ata-pp5020.c	2009-08-18 11:56:58.851400000 -0400
@@ -158,7 +158,10 @@
    and then call ata_dma_finish().
  */
 bool ata_dma_setup(void *addr, unsigned long bytes, bool write) {
-    if (bytes <= 512 || ((unsigned long)addr & 3))
+    if ((unsigned long)addr & 3)
+        return false;
+    /* Require cacheline alignment for reads to prevent interference */
+    if (!write && ((unsigned long)addr & 15))
         return false;
 
 #if ATA_MAX_UDMA > 2
@@ -175,8 +178,6 @@
     else {
         /* Invalidate cache because new data may be present in RAM */
         cpucache_invalidate();
-        /* TODO: Alignment to cache line boundaries should be performed
-           pre/post DMA */
     }
 
     /* Clear pending interrupts so ata_dma_finish() can wait for an