Port status for the FiioX1.

Port Status

feature	status	comments
LCD	0%	TODO.
Music playback	0%	TODO.
FM Radio	0%	TODO.
Recording	0%	TODO.
Power Management	0%	TODO.
Flash	0%	TODO.
SD	0%	TODO.
USB	0%	TODO.
Manual	0%	TODO.
Rockbox Utility	0%	TODO.

Developer information

RAM setup

This information applies to the first hardware version, it may have changed in the other versions: check that.

The RAM datasheet (part of the MCP) is not available, so the only way to know the characteristics was to disassemble the intermediate program loader (IPL) at the beginning of the NAND. Reverse engineering suggests the following configuration is used. In summary: Mobile DDR (LPDDR), 9-bit column by 13-bit rows in 4 bank configuration with 32-bit bus and one chip select (for a total of 64MiB).

Parameter	Value	Unit	Comment
Type	LPDDR		Mobile DDR
Bus-width	32	bit
CS	1		Only uses CS0
Columns	9	bit
Rows	13	bit
Banks	4
CAS	3	tCK	CAS latency
Driver strength	half		Supported by the RAM module
tRAS	42	ns	ACTIVE to PRECHARGE command period to the same bank
tRTP	18	ns	READ to PRECHARGE command period
tRP	18	ns	PRECHARGE command period to the same bank
tRCD	18	ns	ACTIVE to READ or WRITE command period to the same bank
tRC	60	ns	ACTIVE to ACTIVE command period to the same bank
tRRD	12	ns	ACTIVE bank A to ACTIVE bank B command period
tWR	15	ns	WRITE Recovery Time defined by register MR of DDR2 memory
tWTR	1	ns	WRITE to READ command delay
tRFC	31	ns	AUTO-REFRESH command period
tMINSR	<=9	ns	Minimum Self-Refresh / Deep-Power-Down
tXP	2	ns	EXIT-POWER-DOWN to next valid command period
tMRD	2	ns	Load-Mode-Register to next valid command period
tREFI	7.8	us	Refresh period: 4096 refresh cycles/64ms

-- AmauryPouly - 27 Aug 2015