RockChip Nano-D

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Overview

This is the page for the RockChip Nano-D system-on-chip. Based on the fact sheet (attached to this page), it has dual Cortex-M3 with 1MB of SRAM (datasheet says it's splitted between the core but maybe it is accessible by both). It seems to have hardware to help audio decoding, and otherwise features the usual peripherals. This SoC is known to be used in the following players:

• SonyNWE390

System Model

Description

• Processor: ARM Cortex-M3

System Memory Map

The system memory map is consistent with the ARMv7 Architecture, we refer to this document for more information.

Start	End	Name	Description
0x01000000	0x01FFFFFF	IRAM	on-chip RAM
0x20000000	0x3FFFFFFF	SRAM	on-chip RAM
0x40000000	0x5FFFFFFF	Peripherals	on-chip peripherals
0x60000000	0x7FFFFFFF	RAM	RAM (cached)
0x80000000	0x9FFFFFFF	RAM	RAM (write-through)
0xA0000000	0xBFFFFFFF	Device	Shared device space
0xC0000000	0xDFFFFFFF	Device	Non-shared device space
0xE0000000	0xFFFFFFFF	System	System region

The system region contains all the standard ARMv7 devices:

Start	End	Name	Description
0xE000E000	0xE000E00F	ICTAC	Interrupt Controller Type and Auxillary Control
0xE000E010	0xE000E0FF	SysTick	System timer
0xE000E100	0xE000ECFF	NVIC	External Interrupt Controller
0xE000ED00	0xE000ED8F	SCB	System Control Block

The peripherals region contains the following blocks:

Start	End	Name	Description

From ARM Cortex-M3, it has two bit-band regions:

Start	End	Name	Description
0x20000000	0x20100000	SRAM	1MB on-chip RAM region
0x22000000	0x24000000	SRAM	bit-band SRAM alias
0x40000000	0x40100000	Peripheral	1MB peripheral region
0x42000000	0x44000000	Peripheral	bit-band peripheral alias

The RKNano-B seems to use the RAM region for peripherals because it doesn't have external RAM. The following regions are known:

Start	End	Name	Description

USB core

Nothing is known currently.

DFU Mode

copy-paste from NanoB, check this information

Similarly to the Rockchip27xx and RockChipNanoB, it has a USB DFU mode which allows to upload code to the device. This mode is enhanced with respect to the Rockchip27xx since one can send an arbitrary large binary: it must be split up in pieces of 4096 bytes. The payload is encrypted in continuous mode using XOR routine of the Rockchip27xx. The binary is standard Cortex image: it starts with the address of the stack, then 30 entries for the vector table and then the code. As with the Rockchip27xx, the data sent is appended two bytes of CRC. The code is loaded at 0x01000000.

-- AmauryPouly - 01 Jun 2016